UCT/ZE/TEST: expand ZE RMA coverage and fix ze_copy rkey_compare path

src/uct/ze/copy/ze_copy_md.c

@@ -133,6 +133,13 @@ uct_ze_copy_mem_reg(uct_md_h md, void *address, size_t length,
     return UCS_OK;
 }
 
+static ucs_status_t
+uct_ze_copy_mem_dereg(uct_md_h md, const uct_md_mem_dereg_params_t *params)
+{
+    UCT_MD_MEM_DEREG_CHECK_PARAMS(params, 0);
+    return UCS_OK;
+}
+
 static void uct_ze_copy_md_close(uct_md_h uct_md)
 {
     uct_ze_copy_md_t *md = ucs_derived_of(uct_md, uct_ze_copy_md_t);
@@ -275,7 +282,7 @@ static uct_md_ops_t md_ops = {
     .mem_free           = uct_ze_copy_mem_free,
     .mem_advise         = (uct_md_mem_advise_func_t)ucs_empty_function_return_unsupported,
     .mem_reg            = uct_ze_copy_mem_reg,
-    .mem_dereg          = (uct_md_mem_dereg_func_t)ucs_empty_function_return_success,
+    .mem_dereg          = uct_ze_copy_mem_dereg,
     .mem_query          = uct_ze_copy_md_mem_query,
     .mkey_pack          = (uct_md_mkey_pack_func_t)ucs_empty_function_return_success,
     .mem_attach         = (uct_md_mem_attach_func_t)ucs_empty_function_return_unsupported,
@@ -343,6 +350,7 @@ uct_component_t uct_ze_copy_component = {
     .rkey_unpack        = uct_ze_copy_rkey_unpack,
     .rkey_ptr           = (uct_component_rkey_ptr_func_t)ucs_empty_function_return_unsupported,
     .rkey_release       = (uct_component_rkey_release_func_t)ucs_empty_function_return_success,
+    .rkey_compare       = uct_base_rkey_compare,
     .name               = "ze_cpy",
     .md_config = {
         .name       = "ze-copy memory domain",

test/gtest/Makefile.am

@@ -321,7 +321,8 @@ endif
 
 if HAVE_ZE
 gtest_SOURCES += \
-	ucm/ze_hooks.cc
+	ucm/ze_hooks.cc \
+	uct/ze/test_ze.cc
 gtest_CPPFLAGS += \
 	$(ZE_CPPFLAGS)
 gtest_LDFLAGS += \

test/gtest/uct/test_md.cc

@@ -1,6 +1,7 @@
 /**
 * Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2016. ALL RIGHTS RESERVED.
 * Copyright (C) Advanced Micro Devices, Inc. 2016 - 2017. ALL RIGHTS RESERVED.
+* Copyright (C) Intel Corporation, 2026. ALL RIGHTS RESERVED.
 * See file LICENSE for terms.
 */
 
@@ -43,6 +44,7 @@ extern "C" {
                    cuda_ipc, \
                    rocm_cpy, \
                    rocm_ipc, \
+                   ze_cpy, \
                    ib, \
                    ugni, \
                    gdr_copy, \
@@ -276,7 +278,10 @@ bool test_md::is_device_detected(ucs_memory_type_t mem_type)
 {
     return (mem_type != UCS_MEMORY_TYPE_ROCM) &&
            (mem_type != UCS_MEMORY_TYPE_ROCM_MANAGED) &&
-           (mem_type != UCS_MEMORY_TYPE_CUDA_MANAGED);
+           (mem_type != UCS_MEMORY_TYPE_CUDA_MANAGED) &&
+           (mem_type != UCS_MEMORY_TYPE_ZE_HOST) &&
+           (mem_type != UCS_MEMORY_TYPE_ZE_DEVICE) &&
+           (mem_type != UCS_MEMORY_TYPE_ZE_MANAGED);
 }
 
 void test_md::dereg_cb(uct_completion_t *comp)
@@ -536,7 +541,10 @@ UCS_TEST_P(test_md, mem_type_detect_mds) {
                                       slice_length, &mem_attr);
             ASSERT_UCS_OK(status);
             EXPECT_EQ(alloc_mem_type, mem_attr.mem_type);
-            if (alloc_mem_type == UCS_MEMORY_TYPE_CUDA) {
+            if ((alloc_mem_type == UCS_MEMORY_TYPE_CUDA) ||
+                (alloc_mem_type == UCS_MEMORY_TYPE_ZE_HOST) ||
+                (alloc_mem_type == UCS_MEMORY_TYPE_ZE_DEVICE) ||
+                (alloc_mem_type == UCS_MEMORY_TYPE_ZE_MANAGED)) {
                 EXPECT_EQ(buffer_size, mem_attr.alloc_length);
                 EXPECT_EQ(address, mem_attr.base_address);
             } else {
@@ -1190,6 +1198,85 @@ UCS_TEST_SKIP_COND_P(test_md_non_blocking, reg,
 
 UCT_MD_INSTANTIATE_TEST_CASE(test_md_non_blocking)
 
+class test_md_dmabuf : public test_md {
+};
+
+UCS_TEST_P(test_md_dmabuf, mem_query_dmabuf)
+{
+    if ((md_attr().dmabuf_mem_types & md_attr().access_mem_types) == 0) {
+        UCS_TEST_SKIP_R("MD does not expose dmabuf memory query");
+    }
+
+    const size_t size      = ucs_get_page_size();
+    const size_t offsets[] = {0, 128};
+    size_t tested          = 0;
+
+    for (auto mem_type : mem_buffer::supported_mem_types()) {
+        const bool dmabuf_expected = !!(md_attr().dmabuf_mem_types &
+                                        UCS_BIT(mem_type));
+
+        if (!mem_buffer::is_mem_type_supported(mem_type) ||
+            !(md_attr().access_mem_types & UCS_BIT(mem_type))) {
+            UCS_TEST_MESSAGE << "skipping " << ucs_memory_type_names[mem_type]
+                             << " (unsupported on system or MD)";
+            continue;
+        }
+
+        mem_buffer mem_buf(size, mem_type);
+
+        if (!dmabuf_expected) {
+            /* Memory type without dmabuf export: verify the negative and
+             * error paths at offset 0. */
+            uct_md_mem_attr_t mem_attr = {};
+
+            mem_attr.field_mask = UCT_MD_MEM_ATTR_FIELD_MEM_TYPE |
+                                  UCT_MD_MEM_ATTR_FIELD_DMABUF_FD |
+                                  UCT_MD_MEM_ATTR_FIELD_DMABUF_OFFSET;
+
+            ucs_status_t status = uct_md_mem_query(md(), mem_buf.ptr(),
+                                                   mem_buf.size(), &mem_attr);
+            if (status == UCS_OK) {
+                /* MDs may report a valid memory type without a dmabuf fd */
+                EXPECT_EQ(UCT_DMABUF_FD_INVALID, mem_attr.dmabuf_fd);
+            } else {
+                EXPECT_TRUE((status == UCS_ERR_UNSUPPORTED) ||
+                            (status == UCS_ERR_INVALID_ADDR))
+                        << "status=" << ucs_status_string(status);
+            }
+            continue;
+        }
+
+        for (size_t offset : offsets) {
+            uct_md_mem_attr_t mem_attr = {};
+            void *query_ptr = UCS_PTR_BYTE_OFFSET(mem_buf.ptr(), offset);
+
+            mem_attr.field_mask = UCT_MD_MEM_ATTR_FIELD_MEM_TYPE |
+                                  UCT_MD_MEM_ATTR_FIELD_BASE_ADDRESS |
+                                  UCT_MD_MEM_ATTR_FIELD_DMABUF_FD |
+                                  UCT_MD_MEM_ATTR_FIELD_DMABUF_OFFSET;
+
+            ucs_status_t status = uct_md_mem_query(md(), query_ptr,
+                                                   size - offset, &mem_attr);
+            ASSERT_UCS_OK(status);
+
+            EXPECT_EQ(mem_type, mem_attr.mem_type);
+            EXPECT_EQ(mem_buf.ptr(), mem_attr.base_address);
+            EXPECT_EQ((off_t)offset, mem_attr.dmabuf_offset);
+            EXPECT_GE(mem_attr.dmabuf_fd, 0);
+            close(mem_attr.dmabuf_fd);
+        }
+
+        ++tested;
+    }
+
+    if (tested == 0) {
+        UCS_TEST_SKIP_R("MD does not expose dmabuf for any supported memory "
+                        "type");
+    }
+}
+
+UCT_MD_INSTANTIATE_TEST_CASE(test_md_dmabuf)
+
 class test_cuda : public test_md
 {
 };

test/gtest/uct/test_p2p_rma.cc

@@ -1,5 +1,6 @@
 /**
 * Copyright (c) NVIDIA CORPORATION & AFFILIATES, 2001-2014. ALL RIGHTS RESERVED.
+* Copyright (C) Intel Corporation, 2026. ALL RIGHTS RESERVED.
 *
 * See file LICENSE for terms.
 */
@@ -71,8 +72,8 @@ void uct_p2p_rma_test::test_xfer(send_func_t send, size_t length,
 {
     ucs_memory_type_t src_mem_type = UCS_MEMORY_TYPE_HOST;
 
-    if (has_transport("cuda_ipc") ||
-        has_transport("rocm_copy")) {
+    if (has_transport("cuda_ipc") || has_transport("rocm_copy") ||
+        has_transport("ze_copy")) {
         src_mem_type = mem_type;
     }
 

test/gtest/uct/uct_test.h

@@ -4,6 +4,7 @@
 * Copyright (C) UT-Battelle, LLC. 2015. ALL RIGHTS RESERVED.
 * Copyright (C) ARM Ltd. 2017.  ALL RIGHTS RESERVED
 * Copyright (C) Advanced Micro Devices, Inc. 2016 - 2017. ALL RIGHTS RESERVED.
+* Copyright (C) Intel Corporation, 2026. ALL RIGHTS RESERVED.
 * See file LICENSE for terms.
 */
 
@@ -508,6 +509,8 @@ class test_uct_iface_attrs : public uct_test {
 #define UCT_TEST_ROCM_MEM_TYPE_TLS \
     rocm_copy
 
+#define UCT_TEST_ZE_MEM_TYPE_TLS ze_copy
+
 #define UCT_TEST_NO_GPU_MEM_TYPE_TLS \
     UCT_TEST_NO_SELF_TLS, \
     self
@@ -584,6 +587,16 @@ class test_uct_iface_attrs : public uct_test {
     UCS_PP_FOREACH(_UCT_INSTANTIATE_TEST_CASE, _test_case, UCT_TEST_CUDA_MEM_TYPE_TLS)
 
 
+/**
+ * Instantiate the parametrized test case for ZE copy transport.
+ *
+ * @param _test_case  Test case class, derived from uct_test.
+ */
+#define UCT_INSTANTIATE_ZE_TEST_CASE(_test_case) \
+    UCS_PP_FOREACH(_UCT_INSTANTIATE_TEST_CASE, _test_case, \
+                   UCT_TEST_ZE_MEM_TYPE_TLS)
+
+
 /**
  * Instantiate the parametrized test case for all sockaddr CMs.
  *