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    63 repositories

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •936•0•0•2•Updated Jan 16, 2026Jan 16, 2026

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •41•0•0•0•Updated Jan 5, 2026Jan 5, 2026

    • he-soc

      Public
      C
      •
      Other
      •11•32•1•2•Updated Dec 7, 2025Dec 7, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •32•0•0•1•Updated Oct 20, 2025Oct 20, 2025

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •23•0•0•0•Updated Jul 13, 2025Jul 13, 2025

    • hyper_bus

      Public
      VHDL
      •0•0•0•0•Updated Jul 7, 2025Jul 7, 2025

    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      •
      Other
      •874•0•0•1•Updated Jun 3, 2025Jun 3, 2025

    • alsaqr-fpga

      Public
      Makefile
      •3•0•0•0•Updated May 5, 2025May 5, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •87•1•0•0•Updated May 5, 2025May 5, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •44•0•0•0•Updated Jan 14, 2025Jan 14, 2025

    • riscv_nn

      Public
      SystemVerilog
      •
      Other
      •2•3•1•0•Updated Jan 14, 2025Jan 14, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •646•0•0•0•Updated Dec 20, 2024Dec 20, 2024

    • hier-icache

      Public
      SystemVerilog
      •
      Other
      •13•0•0•0•Updated Nov 12, 2024Nov 12, 2024

    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      SystemVerilog
      •
      Apache License 2.0
      •680•0•0•0•Updated Nov 5, 2024Nov 5, 2024

    • riscv-aia

      Public
      AIA IP compliant with the RISC-V AIA spec
      SystemVerilog
      •
      Apache License 2.0
      •12•0•0•0•Updated Oct 15, 2024Oct 15, 2024

    • riscv-iopmp

      Public
      IOPMP IP
      SystemVerilog
      •
      Apache License 2.0
      •7•0•0•1•Updated Oct 15, 2024Oct 15, 2024

    • riscv-iommu

      Public
      IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
      SystemVerilog
      •
      Apache License 2.0
      •29•0•0•0•Updated Oct 15, 2024Oct 15, 2024

    • fpu_interco

      Public
      SystemVerilog
      •
      Other
      •6•0•0•0•Updated Jul 26, 2024Jul 26, 2024

    • Splash-3

      Public
      The Splash-3 benchmark suite
      GLSL
      •30•0•0•0•Updated Jul 16, 2024Jul 16, 2024

    • CHERI-Litmus

      Public
      A tool to run litmus tests on bare-metal hardware
      C
      •
      Other
      •14•0•0•0•Updated Jun 10, 2024Jun 10, 2024

    • Shaheen_PCB

      Public
      HTML
      •
      Other
      •0•0•0•0•Updated May 29, 2024May 29, 2024

    • culsans

      Public
      Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
      C
      •15•0•0•0•Updated May 22, 2024May 22, 2024

    • ace

      Public
      SystemVerilog
      •6•0•0•0•Updated Apr 26, 2024Apr 26, 2024

    • ethernet

      Public
      Ethernet for Al Saqr platform
      SystemVerilog
      •
      MIT License
      •0•0•0•0•Updated Apr 16, 2024Apr 16, 2024

    • padrick

      Public
      Padrick - A Smart Pad-Multiplexer IP Generator for SoCs
      Python
      •
      Apache License 2.0
      •3•0•0•1•Updated Mar 13, 2024Mar 13, 2024

    • apb_adv_timer

      Public
      Advanced timer with APB interface
      SystemVerilog
      •
      Other
      •9•0•0•0•Updated Mar 11, 2024Mar 11, 2024

    • openpiton

      Public
      The OpenPiton Platform
      Assembly
      •255•0•0•0•Updated Feb 28, 2024Feb 28, 2024

    • axi_riscv_atomics

      Public
      AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      •
      Other
      •20•0•0•0•Updated Feb 16, 2024Feb 16, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      •
      Other
      •332•0•0•0•Updated Oct 11, 2023Oct 11, 2023

    • sdio_vip

      Public
      sdiovip
      Verilog
      •0•2•0•0•Updated Sep 15, 2023Sep 15, 2023