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    768 repositories

    • sc2v

      Public
      SystemC to Verilog Synthesizable Subset Translator
      C
      •
      GNU General Public License v2.0
      •7•13•0•1•Updated May 12, 2023May 12, 2023

    • i2c

      Public
      I2C controller core
      Verilog
      •38•51•2•2•Updated Jan 1, 2023Jan 1, 2023

    • jpegencode

      Public
      JPEG Encoder Verilog
      Verilog
      •36•82•2•0•Updated Oct 31, 2022Oct 31, 2022

    • xtea

      Public
      XTEA Crypto Core
      Verilog
      •
      GNU Lesser General Public License v2.1
      •0•4•0•0•Updated Oct 31, 2022Oct 31, 2022

    • des

      Public
      DES/Triple DES IP Cores
      Verilog
      •2•4•0•0•Updated Oct 30, 2022Oct 30, 2022

    • aes_core

      Public
      AES (Rijndael) IP Core
      Verilog
      •3•7•0•0•Updated Oct 30, 2022Oct 30, 2022

    • tiny_aes

      Public
      AES
      Verilog
      •
      Apache License 2.0
      •7•15•0•0•Updated Oct 4, 2022Oct 4, 2022

    • embedded_risc

      Public
      Embedded 32-bit RISC uProcessor with SDRAM Controller
      Verilog
      •6•26•0•0•Updated Sep 2, 2021Sep 2, 2021

    • systemcmd5

      Public
      SystemC/Verilog MD5
      C++
      •5•5•0•0•Updated May 14, 2021May 14, 2021

    • mmu180

      Public
      MMU for Z80 and eZ80
      Verilog
      •5•21•0•0•Updated Mar 4, 2021Mar 4, 2021

    • ethmac

      Public
      Ethernet MAC 10/100 Mbps
      Verilog
      •41•87•2•0•Updated Oct 2, 2019Oct 2, 2019

    • mips_16

      Public
      Educational 16-bit MIPS Processor
      Verilog
      •12•18•0•1•Updated Feb 16, 2019Feb 16, 2019

    • ps2

      Public
      PS2 interface
      Verilog
      •7•18•0•0•Updated Dec 4, 2017Dec 4, 2017

    • minirisc

      Public
      Mini-Risc core
      Verilog
      •8•7•0•0•Updated Dec 4, 2017Dec 4, 2017

    • turbo8051

      Public
      turbo 8051
      Verilog
      •15•30•0•1•Updated Aug 30, 2017Aug 30, 2017

    • freecores.github.io

      Public
      Freecores website
      CSS
      •6•19•1•1•Updated Dec 22, 2016Dec 22, 2016

    • wb_builder

      Public
      WISHBONE Builder
      Perl
      •3•15•0•0•Updated Sep 10, 2016Sep 10, 2016

    • mmuart

      Public
      Simple RS232 UART
      Verilog
      •1•12•0•0•Updated Apr 3, 2016Apr 3, 2016

    • altor32

      Public
      AltOr32 - Alternative Lightweight OpenRisc CPU
      Verilog
      •
      GNU Lesser General Public License v3.0
      •6•4•0•0•Updated Aug 10, 2014Aug 10, 2014

    • test_project

      Public
      No description
      C
      •0•1•0•0•Updated Jul 17, 2014Jul 17, 2014

    • opb_wb_wrapper

      Public
      WB/OPB & OPB/WB Interface Wrapper
      Verilog
      •2•1•0•0•Updated Jul 17, 2014Jul 17, 2014

    • lem1_9min

      Public
      LEM1_9
      VHDL
      •1•0•0•0•Updated Jul 17, 2014Jul 17, 2014

    • avr_core

      Public
      AVR Core
      7•12•0•0•Updated Jul 17, 2014Jul 17, 2014

    • ao486

      Public
      ao486
      C++
      •1•5•1•0•Updated Jul 17, 2014Jul 17, 2014

    • myforthprocessor

      Public
      FORTH processor with Java compiler
      Java
      •6•4•0•0•Updated Jul 17, 2014Jul 17, 2014

    • zx_ula

      Public
      ULA chip for ZX Spectrum
      Verilog
      •4•22•0•0•Updated Jul 17, 2014Jul 17, 2014

    • zpu

      Public
      ZPU - the worlds smallest 32 bit CPU with GCC toolchain
      VHDL
      •4•16•0•0•Updated Jul 17, 2014Jul 17, 2014

    • zorro_to_wishbone_bridge

      Public
      Zorro bus to Wishbone bridge
      0•0•0•0•Updated Jul 17, 2014Jul 17, 2014

    • zet86

      Public
      Zet - The x86 (IA-32) open implementation
      C
      •
      GNU General Public License v3.0
      •4•23•0•0•Updated Jul 17, 2014Jul 17, 2014

    • zbt_sram_controller

      Public
      ZBT SRAM Controller
      VHDL
      •
      Other
      •0•4•0•0•Updated Jul 17, 2014Jul 17, 2014
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