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    161 repositories

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •1.1k•3.5k•1.6k•414•Updated Jul 14, 2026Jul 14, 2026

    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      hardwarerisc-vrv32
      hardwarerisc-vrv32cpucore
      SystemVerilog
      •
      Apache License 2.0
      •771•2k•209•42•Updated Jul 14, 2026Jul 14, 2026

    • mocha

      Public
      CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.
      SystemVerilog
      •19•35•126•22•Updated Jul 13, 2026Jul 13, 2026

    • u-boot

      Public
      "Das U-Boot" Source Tree
      C
      •4.5k•1•0•0•Updated Jul 10, 2026Jul 10, 2026

    • llvm-project

      Public
      The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github pull requests at this …
      C++
      •18k•2•0•0•Updated Jul 10, 2026Jul 10, 2026

    • ot-sku

      Public
      OT SKUs
      Starlark
      •5•0•2•2•Updated Jul 9, 2026Jul 9, 2026

    • style-guides

      Public
      lowRISC Style Guides
      Creative Commons Attribution 4.0 International
      •134•520•19•2•Updated Jul 8, 2026Jul 8, 2026

    • lowrisc-nix

      Public
      lowRISC Nix Packages and Environments
      Nix
      •
      MIT License
      •12•8•1•2•Updated Jul 7, 2026Jul 7, 2026

    • part-number-registry

      Public
      Registry of various part number and ID namespaces that lowRISC controls
      Apache License 2.0
      •1•1•0•0•Updated Jul 7, 2026Jul 7, 2026

    • dvsim

      Public
      DVSim is a build and run system written in Python that runs a variety of EDA tool flows
      Python
      •
      Apache License 2.0
      •19•9•31•2•Updated Jul 1, 2026Jul 1, 2026

    • sail-cheri-riscv

      Public
      CHERI-RISC-V model written in Sail
      Isabelle
      •
      Other
      •25•0•0•0•Updated Jun 28, 2026Jun 28, 2026

    • sail-riscv

      Public
      Sail RISC-V model
      Coq
      •
      Other
      •275•0•0•1•Updated Jun 28, 2026Jun 28, 2026

    • opensbi

      Public
      OpenSBI with CHERI-RISC-V support
      6•0•0•0•Updated Jun 24, 2026Jun 24, 2026

    • busybox

      Public
      Provide a CHERI-enabled busybox port to support minimal Linux userspace builds.
      C
      •
      Other
      •4•0•0•0•Updated Jun 24, 2026Jun 24, 2026

    • linux

      Public
      Linux kernel source tree
      C
      •
      Other
      •63k•1•0•1•Updated Jun 24, 2026Jun 24, 2026

    • qemu

      Public
      Fork of QEMU for development of lowRISC platforms (including OpenTitan)
      C
      •
      Other
      •7k•9•12•6•Updated Jun 19, 2026Jun 19, 2026

    • ftditool

      Public
      A C++ implementation for SPI Flash and GPIO leveraging FTDI MPSSE-enabled chips.
      C++
      •
      Other
      •1•2•0•0•Updated Jun 18, 2026Jun 18, 2026

    • compile-to-core

      Public
      A simple converter that turns a compile.yml file into a FuseSoC core
      Python
      •
      Apache License 2.0
      •1•0•0•0•Updated Jun 11, 2026Jun 11, 2026

    • sonata-software

      Public
      Software, build flows and examples for the Sonata System
      C++
      •
      Apache License 2.0
      •16•14•3•1•Updated Jun 1, 2026Jun 1, 2026

    • riscv-isa-sim

      Public
      RISC-V Functional ISA Simulator
      C
      •
      Other
      •1.1k•20•0•2•Updated May 28, 2026May 28, 2026

    • ariane-ethernet

      Public archive
      open-source Ethenet media access controller for Ariane on Genesys-2
      SystemVerilog
      •
      MIT License
      •11•21•2•0•Updated May 19, 2026May 19, 2026

    • opentitan-provisioning

      Public
      Reference OpenTitan Provisioning Infrastructure
      Go
      •
      Apache License 2.0
      •10•15•17•2•Updated May 18, 2026May 18, 2026

    • cva6-cheri

      Public
      Assembly
      •
      Other
      •11•0•0•0•Updated May 11, 2026May 11, 2026

    • cheribuild

      Public
      Easily build and run CHERI related projects
      Python
      •
      Other
      •58•0•0•0•Updated Apr 29, 2026Apr 29, 2026

    • binutils

      Public
      (Unsupported) lowRISC fork of Binutils
      C
      •
      GNU General Public License v2.0
      •2•0•0•1•Updated Apr 20, 2026Apr 20, 2026

    • sonata-system

      Public
      A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI
      C++
      •
      Apache License 2.0
      •36•54•11•10•Updated Apr 14, 2026Apr 14, 2026

    • ci-actions

      Public
      Reuseable Github Actions for CI workflows in lowRISC projects.
      MIT License
      •0•0•0•0•Updated Apr 14, 2026Apr 14, 2026

    • sail

      Public
      Sail architecture definition language
      Isabelle
      •
      Other
      •159•0•0•0•Updated Feb 27, 2026Feb 27, 2026

    • lowrisc-toolchains

      Public
      UNSUPPORTED INTERNAL toolchain builds
      Shell
      •22•48•3•1•Updated Feb 24, 2026Feb 24, 2026

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      SystemVerilog
      •
      Other
      •851•1•0•0•Updated Feb 6, 2026Feb 6, 2026
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