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    326 repositories

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •67•318•24•9•Updated Jul 13, 2026Jul 13, 2026

    • redmule

      Public
      SystemVerilog
      •
      Other
      •24•109•3•5•Updated Jul 12, 2026Jul 12, 2026

    • gwaihir

      Public
      aka Lago-Mio
      C
      •
      Other
      •3•5•4•8•Updated Jul 12, 2026Jul 12, 2026

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •21•17•5•1•Updated Jul 12, 2026Jul 12, 2026

    • TeraNoC

      Public
      An open-source hybrid Mesh–Crossbar NoC for scalable, low-latency shared-L1-memory clusters with thousands of cores.
      C
      •
      Apache License 2.0
      •8•38•0•2•Updated Jul 11, 2026Jul 11, 2026

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •48•163•3•10•Updated Jul 11, 2026Jul 11, 2026

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      C
      •
      Apache License 2.0
      •7•24•19•0•Updated Jul 11, 2026Jul 11, 2026

    • control-pulp

      Public
      Open-source, hardware/software RISC-V platform designed for on-chip power control
      C
      •
      Other
      •4•9•1•3•Updated Jul 10, 2026Jul 10, 2026

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •15•22•3•12•Updated Jul 10, 2026Jul 10, 2026

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicfpgasimulation
      asicfpgasimulationriscvsystemverilogrtl-design
      Verilog
      •
      Other
      •113•354•23•29•Updated Jul 10, 2026Jul 10, 2026

    • hwpe-ctrl

      Public
      IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •23•8•1•6•Updated Jul 10, 2026Jul 10, 2026

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •59•225•12•10•Updated Jul 10, 2026Jul 10, 2026

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •10•21•0•6•Updated Jul 10, 2026Jul 10, 2026

    • ace

      Public
      SystemVerilog
      •
      Other
      •7•26•0•1•Updated Jul 10, 2026Jul 10, 2026

    • spatz_vpu

      Public
      Spatz vector processing unit
      C
      •
      Apache License 2.0
      •0•0•0•1•Updated Jul 10, 2026Jul 10, 2026

    • cluster_interconnect

      Public
      SystemVerilog
      •
      Other
      •17•17•1•3•Updated Jul 10, 2026Jul 10, 2026

    • dram_rtl_sim

      Public
      SystemVerilog
      •
      Other
      •11•19•1•2•Updated Jul 9, 2026Jul 9, 2026

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •973•23•2•0•Updated Jul 9, 2026Jul 9, 2026

    • ManyRVData

      Public
      This is the repository for CachePool architecture for the ManyRVData project
      C
      •6•3•0•2•Updated Jul 9, 2026Jul 9, 2026

    • magia-sdk

      Public
      C
      •
      Apache License 2.0
      •11•7•5•11•Updated Jul 9, 2026Jul 9, 2026

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •14•39•0•1•Updated Jul 9, 2026Jul 9, 2026

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •62•379•27•10•Updated Jul 9, 2026Jul 9, 2026

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •111•138•18•7•Updated Jul 8, 2026Jul 8, 2026

    • axi_obi

      Public
      SystemVerilog protocol converters between the PULP-platform AXI and OBI IPs
      SystemVerilog
      •
      Other
      •4•5•0•2•Updated Jul 8, 2026Jul 8, 2026

    • clic

      Public
      RISC-V fast interrupt controller
      interruptrisc-vclic
      interruptrisc-vclic
      SystemVerilog
      •
      Apache License 2.0
      •5•35•7•4•Updated Jul 8, 2026Jul 8, 2026

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardware
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •360•1.6k•50•20•Updated Jul 8, 2026Jul 8, 2026

    • unbent

      Public
      SystemVerilog
      •
      Other
      •3•2•0•1•Updated Jul 8, 2026Jul 8, 2026

    • pulp-actions

      Public
      Python
      •
      Apache License 2.0
      •6•11•1•2•Updated Jul 7, 2026Jul 7, 2026

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •40•53•7•4•Updated Jul 7, 2026Jul 7, 2026

    • axi_riscv_atomics

      Public
      AXI Adapter(s) for RISC-V Atomic Operations
      SystemVerilog
      •
      Other
      •23•66•1•5•Updated Jul 6, 2026Jul 6, 2026
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