Merge pull request #416 from AYYAZmayo/main

AYYAZmayo · web-flow · commit 2626a24846df · 2024-10-10T10:49:16.000+05:00
Release_Sim_1.5.7
diff --git a/genesis3/FPGA_PRIMITIVES_MODELS b/genesis3/FPGA_PRIMITIVES_MODELS
@@ -1 +1 @@
-Subproject commit c3b0e742d194e31bd56d20be4640268b02990197
+Subproject commit e6466dbc19bc2c318a9530e00f3c19e10719b0cc
diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc
@@ -7880,7 +7880,7 @@ void collect_clocks (RTLIL::Module* module,
         // WARNING; we may need to handle case where 'keep' attribute is on
         // the I_BUF/O_BUF so that we cannot remove them.
         //
-#if 0
+#if 1
         remove_io_buffers(top_module);
 
         // Bypass the assigns by replacing LHs by RHS. Assigns will be
