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Merge pull request #417 from AYYAZmayo/main
Revert EDA-3292 fix, effecting CLK_BUF inference
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src/synth_rapidsilicon.cc

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@@ -7880,7 +7880,7 @@ void collect_clocks (RTLIL::Module* module,
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// WARNING; we may need to handle case where 'keep' attribute is on
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// the I_BUF/O_BUF so that we cannot remove them.
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//
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#if 1
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#if 0
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remove_io_buffers(top_module);
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// Bypass the assigns by replacing LHs by RHS. Assigns will be

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