rev 1.4: Make tristate ports top-level

[jack-h]

• Break out I/O/T ports to top level, to prevent an issue
  where Xilinx won't infer tristate buffers for bidirectional
  ports into out-of-context compiled IP.
• Expose ethernet Link/activity LEDs

[jack-h]

Check you're happy with the port naming conventions -- I use _i, _o, and _t_o, since the latter is still an output. Maybe simply _t would be better?
I also renamed input reset_i to reset_n_i to make it clear it is active low, and exposed some LEDs (which seem to work on my board).
Obviously this change will break your firmware until you change your instantiation!