perf(codegen): plan switch lowering#1002
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Use wider fixed-stride targets for large pre-Shanghai initcode, account for relaxed labels and taken split destinations, and bound planner candidate evaluation. Expand runtime coverage across every dispatch case and table boundaries.
Compute bucket costs with one counter array and route empty indexed-table entries directly to the default target, avoiding temporary inner allocations and throwaway EVM IR blocks.
Route empty ordinary-MIR buckets through one shared POP-and-default thunk so the preserved switch value cannot disturb internal return addresses. Cover the path through a non-inlined internal sparse switch.
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Selects switch lowering late in the EVM backend after MIR optimization. The planner evaluates ordered linear scans, balanced binary trees, modulo buckets, and dense indexed tables against runtime-gas and deployed-size objectives. Indexed jumps retain their possible targets in block EVM IR and become fixed-stride out-of-line jump stubs only after block layout, preserving CFG transformations while enabling dynamic jumps. Nonconstant or duplicate cases conservatively remain ordered linear scans.