This project is for test study and to understand how Verilog behaves at the logic gate level using Xilinx tools. It is designed to help beginners learn digital logic and simulation.

Folder Structure

• basics/ — Beginner-level RTL examples and exercises
• intermediate/ — Intermediate RTL designs and labs
• advanced/ — Advanced RTL projects or challenges

Each level (basics, intermediate, advanced) contains:

• RTL source files (Verilog)
• Example implementations
• Testbench files (in tb/)

rtl-lab