Name		Name	Last commit message	Last commit date
src		src
test_benches		test_benches
.gitignore		.gitignore
Makefile		Makefile
README.md		README.md

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Verilog-Risc-CPU

A very simple implementation of a RISC-like CPU in Verilog.

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A very simple implementation of a RISC-like CPU in Verilog.

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