Final-year B.Tech (ECE) @ VIT Vellore • ASIC / SoC / RTL Design • Embedded Systems

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• 🎯 Interested in ASIC / SoC Design, RTL Verification, and Hardware Debugging
• 🧠 Strong in Digital Design, FSMs, Timing, Synthesis (DC), STA
• 🔧 Hands-on with Synopsys RTL → GDSII flow + embedded prototyping

Languages: Verilog, SystemVerilog, C, Python
Tools: Synopsys Design Compiler, ModelSim, Quartus, Vivado, Cadence Virtuoso
Domains: RTL Design, Verification, STA, FSM, Digital Systems, Embedded Systems

• Smart IoT Sensor Interface Controller (RTL + SV Verification)
  I2C/SPI/UART/FIFO/Arbiter + low-power modes, verified end-to-end.

• RV32I Single-Cycle RISC-V Processor
  Built core datapath + control, validated with self-checking testbenches.

• ESP32 / Arduino Automation Systems
  RFID + sensors + servo control, cloud logging, real-world integration.

• Strengthening verification (SV testbenches + assertions)
• Improving STA & synthesis depth for industry-level RTL

Open to RTL / ASIC / SoC / FPGA opportunities • Bengaluru / Hyderabad / Pune (India)