Memory Management System Simulation This project simulates a memory management system in an operating system, showcasing key concepts such as paging, address translation, and page replacement algorithms. It combines a two-level page table for virtual memory management with a Translation Lookaside Buffer (TLB) to speed up address translation. Additionally, the project incorporates the clock algorithm for efficient page replacement, considering both reference and dirty bits.
Key features include:
Address Translation: Translates virtual addresses into physical addresses using a two-level page table and TLB.
TLB Simulation: Caches recent translations to improve memory access speed, with statistics for TLB hits and misses.
Page Replacement: Handles page faults using the clock algorithm, simulating real-world memory management strategies.
Page Fault Statistics: Tracks page faults, hits, and the overall hit rate to evaluate system performance.
This simulation is designed to demonstrate fundamental OS memory management techniques, making it an ideal project for showcasing proficiency in OS concepts such as virtual memory, address translation, and page replacement algorithms.