Currently — designing analog front-end OTA architectures for next-generation sensing systems. Noise floor, gain-bandwidth, PVT robustness. Also building a Python bitstream analysis toolchain for sigma-delta ADC verification: FFT-based SNDR, ENOB, and noise floor extraction.
| Project | Domain | Notes |
|---|---|---|
| 2nd-Order Σ-Δ Modulator | ADC · AMS |
Loop filter, 1-bit quantizer, DAC feedback. SNDR/ENOB via custom Python tooling. Verified against MATLAB model. |
| Analog Front-End Chain | AFE · Sensor |
Instrumentation input, PGA, anti-alias filter. High-resolution low-frequency sensing. |
| OTA Design | Amplifier · Spectre |
Differential OTA — gain, phase margin, slew rate. Full PVT corner simulation. |
| Latched Comparator | Mixed-Signal |
Strong-arm latch. Offset, metastability, regeneration time characterized. Σ-Δ quantizer block. |
| FFT Processor | FPGA · Xilinx |
Fixed-point pipelined FFT on ARTY A7. Real-time spectral analysis of ADC output. |
Σ-Δ Modulators — continuous-time, high-order, multi-bit architectures
OTA Topologies — folded-cascode, recycling, current-mirror variants
Bandgap References — curvature-corrected, low-noise design
AMS Co-Simulation — Verilog-AMS, mixed-domain verification
Compute-in-Memory — mixed-signal ML accelerators
Intelligent Sensing — edge inference, ADC-DSP co-design
SCHEMATIC / SIM · Cadence Virtuoso · Spectre · LTSpice · Xschem
LAYOUT / VERIFY · Virtuoso Layout · Assura DRC/LVS · Magic VLSI
HDL / FPGA · Verilog · SystemVerilog · VHDL · Xilinx Vivado
ANALYSIS · MATLAB · Simulink · Python
The analog designer's job is not to fight physics — it is to bend the tradeoffs in your favor.