Add NXP S32K5 Cortex-R52 machine#3
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Signed-off-by: Chao Liu <chao.liu@processmission.com>
Signed-off-by: Chao Liu <chao.liu@processmission.com>
Signed-off-by: Chao Liu <chao.liu@processmission.com>
Signed-off-by: Chao Liu <chao.liu@processmission.com>
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Codex Review: Didn't find any major issues. Swish! Reviewed commit: ℹ️ About Codex in GitHubYour team has set up Codex to review pull requests in this repo. Reviews are triggered when you
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Document the S32K566 Cortex-R52 machine, including the implemented devices, memory map, direct RTOS boot command, LPUART console wiring, test command, and current firmware/Linux limitations. Signed-off-by: Chao Liu <chao.liu@processmission.com>
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| const int timer_irq[] = { | ||
| [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | ||
| [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | ||
| [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | ||
| }; |
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For S32K5 Zephyr/R52 images that use the secure physical architected timer (the board DTS exposes PPI 13 / INTID 29 as the first arm,armv8-timer interrupt), this table never connects the CPU's GTIMER_SEC output to the GIC. The guest can program CNTPS and enable IRQ 29, but QEMU will never raise it, so the system tick stalls even though the counter and GIC are present; add the GTIMER_SEC mapping to ARCH_TIMER_S_EL1_IRQ here.
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Summary
s32k566-cvb-r52Cortex-R52 machine, qtest coverage, and system documentation.Validation
git diff --check origin/devel..HEADninja -C build qemu-system-arm tests/qtest/s32k5-testmeson test -C build qtest-arm/s32k5-test --print-errorlogsNotes
This PR covers the verified Zephyr/RTOS S32K566 model. Public NXP S32K566 Linux and firmware-chain inputs were not found, so firmware boot and Linux boot are documented as unsupported in this version.