[Bouffalo lab] Improve BL702/BL702L execution efficiency by updating the linker file #38878
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PR #38878: Size comparison from 7c2d0ea to 86333fe Increases above 0.2%:
Full report (74 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
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PR #38878: Size comparison from b16122c to 8d8fd3d Full report (73 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
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andy31415
approved these changes
May 12, 2025
Contributor
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@wy-hh the summary could be make more clear: why is this more efficient? What did you change in the linker script and for what reason? |
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PR #38878: Size comparison from ad9b873 to 591a9b0 Full report (73 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
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Contributor
Author
Updated. |
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PR #38878: Size comparison from 70e5039 to 591a9b0 Full report (73 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
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andy31415
approved these changes
May 14, 2025
wy-hh
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May 15, 2025
… the linker file (project-chip#38878) * [Bouffalo lab] configure memory region of Thread task stack on BL702/BL702L * Restyled by clang-format --------- Co-authored-by: Restyled.io <[email protected]> Co-authored-by: Andrei Litvin <[email protected]>
wy-hh
added a commit
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May 15, 2025
…pdate BL702/BL702L linker file to improve execution and fix bl616 wifi scan (#4) * [bouffalo lab] Add/update platform configuration to track psram/wifi section for CI build report (project-chip#38865) * [bouffalo lab] Update reference partition table to increase size of P… (project-chip#38875) * [bouffalo lab] Update reference partition table to increase size of PSM region * Restyled by prettier-markdown --------- Co-authored-by: Restyled.io <[email protected]> * [Bouffalo lab] Improve BL702/BL702L execution efficiency by updating the linker file (project-chip#38878) * [Bouffalo lab] configure memory region of Thread task stack on BL702/BL702L * Restyled by clang-format --------- Co-authored-by: Restyled.io <[email protected]> Co-authored-by: Andrei Litvin <[email protected]> * [bouffalo lab] fix bl616 wifi scan operation with/without specified ssid (project-chip#38877) * [bouffalo lab] fix bl616 wifi scan operation with/without specified ssid * Restyled by clang-format * check ssid length before * Verify SSID length prior to copying and correct pScanResult reference handling when SSID is specified. * Restyled by clang-format * remove +1 for mScanSSID * Restyled by clang-format --------- Co-authored-by: Restyled.io <[email protected]> * update documents after cherry-pick --------- Co-authored-by: Restyled.io <[email protected]> Co-authored-by: Andrei Litvin <[email protected]>
heinsaar
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to heinsaar/connectedhomeip
that referenced
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May 15, 2025
… the linker file (project-chip#38878) * [Bouffalo lab] configure memory region of Thread task stack on BL702/BL702L * Restyled by clang-format --------- Co-authored-by: Restyled.io <[email protected]> Co-authored-by: Andrei Litvin <[email protected]>
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BL702/BL702L has SRAM and PSRAM for RAM, and SRAM has faster access speed than PSRAM.
Update linker file to try to put more data/bss data in SRAM, not PSRAM, to improve memory access speed.
Testing
targets:
bouffalolab-bl704ldk-light-thread-littlefsbouffalolab-bl706dk-light-thread-littlefstest commands:
./chip-tool pairing ble-thread 3 hex:<dataset> 20202021 3840./chip-tool onoff toggle 2 1