v0.4.0
Pre-release
Pre-release
Added
- Hardware compilation with Verilator
- Software implementation of a matrix multiplication kernel
Changed
- The
riscv_tests_simcMakefile target was deprecated. The riscv-tests are now run with the Verilated design, which can be called through theriscv_tests_simvMakefile target. - The operand queues now take as a parameter the type conversions they support (currently,
SupportIntExt2,SupportIntExt4, andSupportIntExt8) - The Vector Multiplier unit now has independent pipelines for each element width.