axi_demux: Move typedef outside generate for VCS

Author: andreaskurth

CHANGELOG.md

@@ -17,6 +17,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
   has a single bit, and both values were correctly handled in synthesis.  However, when starting
   simulation, the signal has an undefined value, and ModelSim threw warnings that this violated the
   `unique` condition.
+- `axi_demux`: Move `typedef` outside `generate` for compatibility with VCS.
 - `axi_id_prepend`:
   - Fix text of some assertion messages.
   - Fix case of prepending a single-bit ID.

src/axi_demux.sv

@@ -51,24 +51,25 @@ module axi_demux #(
 
   localparam int unsigned IdCounterWidth = $clog2(MaxTrans);
 
+  //--------------------------------------
+  // Typedefs for the FIFOs / Queues
+  //--------------------------------------
+  typedef logic [AxiIdWidth-1:0] axi_id_t;
+  typedef struct packed {
+    aw_chan_t aw_chan;
+    select_t  aw_select;
+  } aw_chan_select_t;
+  typedef struct packed {
+    ar_chan_t ar_chan;
+    select_t  ar_select;
+  } ar_chan_select_t;
+
   // pass through if only one master port
   if (NoMstPorts == 32'h1) begin : gen_no_demux
     assign mst_reqs_o[0] = slv_req_i;
     assign slv_resp_o    = mst_resps_i;
   // other non degenerate cases
   end else begin : gen_demux
-    //--------------------------------------
-    // Typedefs for the Fifo's / Queues
-    //--------------------------------------
-    typedef logic [AxiIdWidth-1:0] axi_id_t;
-    typedef struct packed {
-      aw_chan_t aw_chan;
-      select_t  aw_select;
-    } aw_chan_select_t;
-    typedef struct packed {
-      ar_chan_t ar_chan;
-      select_t  ar_select;
-    } ar_chan_select_t;
 
     //--------------------------------------
     //--------------------------------------