v0.21.0

Changes since 0.20.0

Added

• axi_serializer: serialize transactions with different IDs to the same ID.

Changed

• axi_modify_address:
  • Simplify redundant slv_resp_t and mst_resp_t parameters to single axi_resp_t parameter.
  • Remove unnecessary slv_a{r,w}_addr_o outputs, which were fed back from the slv_req_i inputs.
    Those signals can instead be derived outside axi_modify_address.
• axi_modify_address_intf:
  • Change name of slave port to slv and master port to mst and change name of associated
    parameters to align them with repository conventions.
  • Change type of parameters to int unsigned because their values are unsigned.
  • Add parameters for data, ID, and user width to avoid derivation from interface, which is
    incompatible with many tools.
  • Add missing I/O suffixes to port names and align them with axi_modify_address.

Fixed

• axi_modify_address_intf: Fix type parameters passed to actual implementation.

v0.20.0

Changes since 0.19.0

Added

• axi_pkg: Add wrap_boundary function to calculate the boundary of a wrapping burst.
• axi_test: The random AXI master rand_axi_master can now emit wrapping bursts (but does not do
  so by default). Three new parameters control the burst types of the emitted transactions; not
  setting those parameters means the random master behaves as it did before this change.
• Interface AXI_BUS_DV: Add Monitor modport, in which all signals are inputs.
• axi/assign.svh: Add AXI_ASSIGN_MONITOR macro, which assigns an AXI_BUS to an
  AXI_BUS_DV.Monitor.
• Package axi_test: Add axi_scoreboard class, which checks that data read from a memory address
  matches data written to that address.

Changed

• axi_pkg:
  • The beat_addr function now supports all burst types. Due to this, the function has two new
    arguments (the length and type of the burst).
  • The beat_upper_byte and beat_lower_byte functions internally call beat_addr, so they have
    two new arguments as well.

v0.19.0

Changes since 0.18.1

Changed

• axi_lite_to_axi: Expose AxCACHE signals. It is now possible to define the cache signal of
  AXI transactions coming out of this module by driving the added slv_aw_cache_i and
  slv_ar_cache_i inputs. To retain the behavior prior to this change, tie those two inputs to
  zero.

v0.18.1

Changes since 0.18.0

Fixed

• axi_modify_address: Fix unconnected w_valid.
• axi_dw_converter: Fix internal inversion of up- and downconversion, which led to incorrect lane
  steering and serialization.
• rand_axi_master (in axi_test): In ATOP mode, this module could get stuck receiving an R beat
  when only writes (without ATOP read responses) were left to complete. This has been fixed.
• assign.svh: Remove spurious semicolons.
• axi_lite_to_apb: Fix message of assertion checking the strobe width.

v0.18.0

Changes since 0.17.0

Added

• axi_dw_converter: a data width converter between AXI interfaces of any data width. Depending on
  its parametrization, this module instantiates one of the following:
  • axi_dw_downsizer: a data width converter between a wide AXI master and a narrower slave.
  • axi_dw_upsizer: a data width converter between a narrow AXI master and a wider slave.

v0.17.0

Changes since 0.16.3

Added

• Add axi_isolate to isolate downstream slaves from receiving new transactions.

Changed

• axi_lite_to_axi: Add mandatory AxiDataWidth parameter to enable fix mentioned below.

Fixed

• Improve compatibility with Xcelium:
  • by removing unsupported hierarchical argument to $bits() function in axi_lite_to_axi;
  • by removing unsupported struct assignment in axi_lite_demux.

v0.16.3

Changes since 0.16.2

Changed

• axi_err_slv: Add optional parameter to define data returned by read response. The parameter
  defaults to a 64-bit value, so buses with data width larger than or equal to 64 bit see an
  additional 32-bit value in error responses compared to the prior version. Other than that, this
  change is fully backward compatible.

v0.16.2

Changes since 0.16.1

Fixed

• axi_atop_filter: Fix underflow in counter for AxiMaxWriteTxns = 1.

v0.16.1

Changes since 0.16.0

Fixed

• Remove whitespace in and semicolon after macro calls.
• axi_intf: Improve Verilator compatibility by disabling unsupported assertions.

v0.16.0

Changes since 0.15.1

Added

• axi_cdc_intf: Add interface variant of AXI clock domain crossing.

Fixed

• axi_cdc: Remove unused global import axi_pkg::*.
• axi_intf: Remove global import axi_pkg::* and explicitly use symbols from axi_pkg.
• axi_lite_cut_intf: Add missing assigns to and from interface ports.
• tb_axi_cdc:
  • Remove global import axi_pkg::*.
  • Define channels with AXI_TYPEDEF macros instead of local typedefs.

Removed

• Remove unused AXI_ARBITRATION and AXI_ROUTING_RULES interfaces.