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Maurus Item
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Switched voting macros to use version in /include and removed local header file.
1 parent 1413b1f commit 23f45e3

10 files changed

+54
-144
lines changed

‎Bender.yml

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@ sources:
2727
- rtl/hsiao_ecc/hsiao_ecc_cor.sv
2828
- rtl/time_redundancy/retry_interface.sv
2929
- rtl/time_redundancy/rr_arb_tree_lock.sv
30-
- rtl/time_redundancy/voters.svh
3130
- rtl/TMR_voter.sv
3231
- rtl/TMR_voter_fail.sv
3332
- rtl/TMR_word_voter.sv

‎rtl/time_redundancy/redundancy_controller.sv

Lines changed: 7 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@
1010
// be consumed and the condition for switching can not be reached.
1111
// Switching back to the redundant mode will unstall the setup.
1212

13-
`include "voters.svh"
13+
`include "redundancy_cells/voters.svh"
1414
`include "common_cells/registers.svh"
1515

1616
module redundancy_controller # (
@@ -80,14 +80,8 @@ module redundancy_controller # (
8080
end
8181
end
8282

83-
// State Voting Logic
84-
if (InternalRedundancy) begin : gen_state_voters
85-
`VOTE3to3(enable_v, enable_d);
86-
`VOTE3to3(counter_v, counter_d);
87-
end else begin
88-
assign enable_d = enable_v;
89-
assign counter_d = counter_v;
90-
end
83+
`VOTEXX(REP, enable_v, enable_d);
84+
`VOTEXX(REP, counter_v, counter_d);
9185

9286
// Generate default case
9387
for (genvar r = 0; r < REP; r++) begin: gen_default_state
@@ -116,16 +110,9 @@ module redundancy_controller # (
116110
end
117111

118112
// Output voting logic
119-
if (InternalRedundancy) begin: gen_output_voters
120-
`VOTE3to1(enable_ov, enable_o);
121-
`VOTE3to1(valid_ov, valid_o);
122-
`VOTE3to1(ready_ov, ready_o);
123-
`VOTE3to1(busy_ov, busy_o);
124-
end else begin: gen_output_passthrough
125-
assign enable_o = enable_ov[0];
126-
assign valid_o = valid_ov[0];
127-
assign ready_o = ready_ov[0];
128-
assign busy_o = busy_ov[0];
129-
end
113+
`VOTEX1(REP, enable_ov, enable_o);
114+
`VOTEX1(REP, valid_ov, valid_o);
115+
`VOTEX1(REP, ready_ov, ready_o);
116+
`VOTEX1(REP, busy_ov, busy_o);
130117

131118
endmodule

‎rtl/time_redundancy/retry_inorder_start.sv

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,12 @@
1313
// but at the wronge place or time.
1414

1515
`include "common_cells/registers.svh"
16-
`include "voters.svh"
16+
17+
`define INCREMENT_WITH_PARITY(input_signal, output_signal) \
18+
begin \
19+
output_signal[$bits(input_signal)-2:0] = input_signal[$bits(input_signal)-2:0] + 1; \
20+
output_signal[$bits(input_signal)-1] = ^output_signal[$bits(input_signal)-2:0]; \
21+
end
1722

1823
module retry_inorder_start # (
1924
parameter type DataType = logic,

‎rtl/time_redundancy/retry_start.sv

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,12 @@
1717
// If you need in-order for pipelined processes have a look at retry_inorder instead.
1818

1919
`include "common_cells/registers.svh"
20-
`include "voters.svh"
20+
21+
`define INCREMENT_WITH_PARITY(input_signal, output_signal) \
22+
begin \
23+
output_signal[$bits(input_signal)-2:0] = input_signal[$bits(input_signal)-2:0] + 1; \
24+
output_signal[$bits(input_signal)-1] = ^output_signal[$bits(input_signal)-2:0]; \
25+
end
2126

2227
module retry_start # (
2328
parameter type DataType = logic,

‎rtl/time_redundancy/time_DMR_end.sv

Lines changed: 8 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@
3232
// This can for example be used with the rr_arb_tree_lock module, but other implementations are
3333
// permissible.
3434

35-
`include "voters.svh"
35+
`include "redundancy_cells/voters.svh"
3636
`include "common_cells/registers.svh"
3737

3838
module time_DMR_end # (
@@ -205,11 +205,7 @@ module time_DMR_end # (
205205
end
206206

207207
// State Voting Logic
208-
if (InternalRedundancy) begin: gen_state_voters
209-
`VOTE3to3ENUM(state_v, state_d);
210-
end else begin: gen_state_passthrough
211-
assign state_d = state_v;
212-
end
208+
`VOTEXX(REP, state_v, state_d);
213209

214210
// State Storage
215211
`FF(state_q, state_d, state_b);
@@ -271,13 +267,8 @@ module time_DMR_end # (
271267
end
272268

273269
// State Voting Logic
274-
if (InternalRedundancy) begin : gen_lock_voters
275-
`VOTE3to3(lock_v, lock_d);
276-
`VOTE3to3(counter_v, counter_d);
277-
end else begin: gen_lock_passthrough
278-
assign counter_d = counter_v;
279-
assign lock_d = lock_v;
280-
end
270+
`VOTEXX(REP, lock_v, lock_d);
271+
`VOTEXX(REP, counter_v, counter_d);
281272

282273
assign lock_o = lock_d[0];
283274

@@ -371,16 +362,9 @@ module time_DMR_end # (
371362
///////////////////////////////////////////////////////////////////////////////////////////////////
372363
// Output Voting
373364

374-
if (InternalRedundancy) begin: gen_output_voters
375-
`VOTE3to1(ready_ov, ready_o);
376-
`VOTE3to1(valid_ov, valid_o);
377-
`VOTE3to1(needs_retry_ov, needs_retry_o);
378-
`VOTE3to1(fault_detected_ov, fault_detected_o);
379-
end else begin: gen_output_passthrough
380-
assign ready_o = ready_ov[0];
381-
assign valid_o = valid_ov[0];
382-
assign needs_retry_o = needs_retry_ov[0];
383-
assign fault_detected_o = fault_detected_ov[0];
384-
end
365+
`VOTEX1(REP, ready_ov, ready_o);
366+
`VOTEX1(REP, valid_ov, valid_o);
367+
`VOTEX1(REP, needs_retry_ov, needs_retry_o);
368+
`VOTEX1(REP, fault_detected_ov, fault_detected_o);
385369

386370
endmodule

‎rtl/time_redundancy/time_DMR_start.sv

Lines changed: 13 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,15 @@
3232
// This can for example be used with the rr_arb_tree_lock module, but other implementations are
3333
// permissible.
3434

35-
`include "voters.svh"
35+
`include "redundancy_cells/voters.svh"
3636
`include "common_cells/registers.svh"
3737

38+
`define INCREMENT_WITH_PARITY(input_signal, output_signal) \
39+
begin \
40+
output_signal[$bits(input_signal)-2:0] = input_signal[$bits(input_signal)-2:0] + 1; \
41+
output_signal[$bits(input_signal)-1] = ^output_signal[$bits(input_signal)-2:0]; \
42+
end
43+
3844
module time_DMR_start # (
3945
// The data type you want to send through / replicate
4046
parameter type DataType = logic,
@@ -136,15 +142,9 @@ module time_DMR_start # (
136142
end
137143

138144
// State Voting Logic
139-
if (InternalRedundancy) begin : gen_state_voters
140-
`VOTE3to3ENUM(state_v, state_d);
141-
`VOTE3to3(id_v, id_d);
142-
`VOTE3to3(data_v, data_d);
143-
end else begin: gen_state_passthrough
144-
assign state_d = state_v;
145-
assign data_d = data_v;
146-
assign id_d = id_v;
147-
end
145+
`VOTEXX(REP, state_v, state_d);
146+
`VOTEXX(REP, id_v, id_d);
147+
`VOTEXX(REP, data_v, data_d);
148148

149149
// Generate default cases
150150
for (genvar r = 0; r < REP; r++) begin: gen_default_state
@@ -182,14 +182,8 @@ module time_DMR_start # (
182182
assign data_o = data_d[0];
183183
assign id_o = id_d[0];
184184

185-
if (InternalRedundancy) begin: gen_output_voters
186-
`VOTE3to1(next_id_ov, next_id_o);
187-
`VOTE3to1(ready_ov, ready_o);
188-
`VOTE3to1(valid_ov, valid_o);
189-
end else begin: gen_output_passthrough
190-
assign next_id_o = next_id_ov[0];
191-
assign ready_o = ready_ov[0];
192-
assign valid_o = valid_ov[0];
193-
end
185+
`VOTEX1(REP, next_id_ov, next_id_o);
186+
`VOTEX1(REP, ready_ov, ready_o);
187+
`VOTEX1(REP, valid_ov, valid_o);
194188

195189
endmodule

‎rtl/time_redundancy/time_TMR_end.sv

Lines changed: 8 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
// This can for example be used with the rr_arb_tree_lock module, but other implementations are
2323
// permissible.
2424

25-
`include "voters.svh"
25+
`include "redundancy_cells/voters.svh"
2626
`include "common_cells/registers.svh"
2727

2828
module time_TMR_end # (
@@ -259,11 +259,7 @@ module time_TMR_end # (
259259
end
260260

261261
// State Voting Logic
262-
if (InternalRedundancy) begin : gen_state_voters
263-
`VOTE3to3ENUM(state_v, state_d);
264-
end else begin: gen_state_passthrough
265-
assign state_d = state_v;
266-
end
262+
`VOTEXX(REP, state_v, state_d);
267263

268264
// Generate default cases
269265
for (genvar r = 0; r < REP; r++) begin: gen_default_state
@@ -386,11 +382,7 @@ module time_TMR_end # (
386382
end
387383

388384
// State Voting Logic
389-
if (InternalRedundancy) begin : gen_state_voters
390-
`VOTE3to3ENUM(state_v, state_d);
391-
end else begin: gen_state_passthrough
392-
assign state_d = state_v;
393-
end
385+
`VOTEXX(REP, state_v, state_d);
394386

395387
// Generate default cases
396388
for (genvar r = 0; r < REP; r++) begin: gen_default_state
@@ -464,13 +456,8 @@ module time_TMR_end # (
464456
end
465457

466458
// State Voting Logic
467-
if (InternalRedundancy) begin: gen_lock_voters
468-
`VOTE3to3(lock_v, lock_d);
469-
`VOTE3to3(counter_v, counter_d);
470-
end else begin: gen_lock_passthrough
471-
assign counter_d = counter_v;
472-
assign lock_d = lock_v;
473-
end
459+
`VOTEXX(REP, lock_v, lock_d);
460+
`VOTEXX(REP, counter_v, counter_d);
474461

475462
assign lock_o = lock_d[0];
476463

@@ -513,14 +500,8 @@ module time_TMR_end # (
513500
///////////////////////////////////////////////////////////////////////////////////////////////////
514501
// Output Voting
515502

516-
if (InternalRedundancy) begin : gen_output_voters
517-
`VOTE3to1(ready_ov, ready_o);
518-
`VOTE3to1(valid_ov, valid_o);
519-
`VOTE3to1(fault_detected_ov, fault_detected_o);
520-
end else begin: gen_output_passthrough
521-
assign ready_o = ready_ov[0];
522-
assign valid_o = valid_ov[0];
523-
assign fault_detected_o = fault_detected_ov[0];
524-
end
503+
`VOTEX1(REP, ready_ov, ready_o);
504+
`VOTEX1(REP, valid_ov, valid_o);
505+
`VOTEX1(REP, fault_detected_ov, fault_detected_o);
525506

526507
endmodule

‎rtl/time_redundancy/time_TMR_start.sv

Lines changed: 6 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@
2222
// This can for example be used with the rr_arb_tree_lock module, but other implementations are
2323
// permissible.
2424

25-
`include "voters.svh"
25+
`include "redundancy_cells/voters.svh"
2626
`include "common_cells/registers.svh"
2727

2828
module time_TMR_start # (
@@ -118,15 +118,9 @@ module time_TMR_start # (
118118
end
119119

120120
// State Voting Logic
121-
if (InternalRedundancy) begin: gen_state_voters
122-
`VOTE3to3ENUM(state_v, state_d);
123-
`VOTE3to3(id_v, id_d);
124-
`VOTE3to3(data_v, data_d);
125-
end else begin: gen_state_passthrough
126-
assign state_d = state_v;
127-
assign data_d = data_v;
128-
assign id_d = id_v;
129-
end
121+
`VOTEXX(REP, state_v, state_d);
122+
`VOTEXX(REP, id_v, id_d);
123+
`VOTEXX(REP, data_v, data_d);
130124

131125
// Generate default cases
132126
for (genvar r = 0; r < REP; r++) begin: gen_default_state
@@ -168,12 +162,7 @@ module time_TMR_start # (
168162
assign data_o = data_d[0];
169163
assign id_o = id_d[0];
170164

171-
if (InternalRedundancy) begin: gen_output_voters
172-
`VOTE3to1(ready_ov, ready_o);
173-
`VOTE3to1(valid_ov, valid_o);
174-
end else begin: gen_output_voters
175-
assign ready_o = ready_ov[0];
176-
assign valid_o = valid_ov[0];
177-
end
165+
`VOTEX1(REP, ready_ov, ready_o);
166+
`VOTEX1(REP, valid_ov, valid_o);
178167

179168
endmodule

‎rtl/time_redundancy/voters.svh

Lines changed: 0 additions & 33 deletions
This file was deleted.

‎src_files.yml

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,6 @@ redundancy_cells:
1111
lowrisc_ecc/prim_secded_72_64_enc.sv,
1212
rtl/time_redundancy/retry_interface.sv
1313
rtl/time_redundancy/rr_arb_tree_lock.sv
14-
rtl/time_redundancy/voters.svh
1514
rtl/TMR_voter.sv,
1615
rtl/TMR_voter_fail.sv,
1716
rtl/TMR_word_voter,

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