@@ -176,14 +176,14 @@ module rr_arb_tree_lock #(
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`ifndef VERILATOR
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lock : assert property (
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@ (posedge clk_i) LockIn | - > req_o && ! gnt_i | => idx_o == $past (idx_o)) else
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- $fatal (1 , " Lock implies same arbiter decision in next cycle if output is not \
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+ $error (1 , " Lock implies same arbiter decision in next cycle if output is not \
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ready." );
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logic [NumIn- 1 : 0 ] req_tmp;
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assign req_tmp = req_q & req_i;
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lock_req: assume property (
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@ (posedge clk_i) LockIn | - > lock_d | => req_tmp == req_q) else
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- $fatal (1 , " It is disallowed to deassert unserved request signals when LockIn is \
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+ $error (1 , " It is disallowed to deassert unserved request signals when LockIn is \
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enabled." );
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`endif
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// pragma translate_on
@@ -353,30 +353,30 @@ module rr_arb_tree_lock #(
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`ifndef XSIM
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initial begin : p_assert
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assert (NumIn)
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- else $fatal (1 , " Input must be at least one element wide." );
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+ else $error (1 , " Input must be at least one element wide." );
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assert (! (LockIn && ExtPrio))
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- else $fatal (1 ," Cannot use LockIn feature together with external ExtPrio." );
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+ else $error (1 ," Cannot use LockIn feature together with external ExtPrio." );
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end
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hot_one : assert property (
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@ (posedge clk_i) $onehot0 (gnt_o))
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- else $fatal (1 , " Grant signal must be hot1 or zero." );
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+ else $error (1 , " Grant signal must be hot1 or zero." );
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gnt0 : assert property (
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@ (posedge clk_i) | gnt_o | - > gnt_i)
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- else $fatal (1 , " Grant out implies grant in." );
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+ else $error (1 , " Grant out implies grant in." );
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gnt1 : assert property (
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@ (posedge clk_i) req_o | - > gnt_i | - > | gnt_o)
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- else $fatal (1 , " Req out and grant in implies grant out." );
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+ else $error (1 , " Req out and grant in implies grant out." );
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gnt_idx : assert property (
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@ (posedge clk_i) req_o | - > gnt_i | - > gnt_o[idx_o])
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- else $fatal (1 , " Idx_o / gnt_o do not match." );
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+ else $error (1 , " Idx_o / gnt_o do not match." );
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req1 : assert property (
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@ (posedge clk_i) req_o | - > | req_i)
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- else $fatal (1 , " Req out implies req in." );
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+ else $error (1 , " Req out implies req in." );
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lock2 : assert property (
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@ (posedge clk_i) disable iff (! rst_ni) lock_rr_q | - > idx_o == $past (idx_o))
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