coresight: cortex_m: gracefully handle inaccessible core after reset#1953
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fbnors wants to merge 1 commit intopyocd:mainfrom
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coresight: cortex_m: gracefully handle inaccessible core after reset#1953fbnors wants to merge 1 commit intopyocd:mainfrom
fbnors wants to merge 1 commit intopyocd:mainfrom
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When performing a post-reset check in `_inner_reset` to ensure the core is not halted, `get_state()` reads the DHCSR register via SWD. On certain MCUs (like the LPC55S28), the SWD link may drop or become temporarily inaccessible immediately after a reset, causing `get_state()` to throw a TransferFaultError. Previously, this unhandled exception would bubble up and cause the flash operation to crash with a fatal status 1 exit code, even if the flash and reset were otherwise successful. This adds a `try/except` block around the state check in `_inner_reset()` to catch `exceptions.Error`. If the core state cannot be read or resumed, it logs a warning instead of aborting the entire command.
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When performing a post-reset check in
_inner_resetto ensure the core is not halted,get_state()reads the DHCSR register via SWD. On certain MCUs (like the LPC55S28), the SWD link may drop or become temporarily inaccessible immediately after a reset, causingget_state()to throw a TransferFaultError.Previously, this unhandled exception would bubble up and cause the flash operation to crash with a fatal status 1 exit code, even if the flash and reset were otherwise successful.
This adds a
try/exceptblock around the state check in_inner_reset()to catchexceptions.Error. If the core state cannot be read or resumed, it logs a warning instead of aborting the entire command.