[training] skip Dtensor/TP integration test pending solution#4059
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[training] skip Dtensor/TP integration test pending solution#4059danielvegamyhre wants to merge 1 commit intomainfrom
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/ao/4059
Note: Links to docs will display an error until the docs builds have been completed. ❌ 2 New Failures, 6 PendingAs of commit 4264158 with merge base 77f23d0 ( NEW FAILURES - The following jobs have failed:
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… on ROCm (#3992) * [ROCm] Enable FSDP2 Float8 and affine quantized tensor parallel tests on ROCm Remove blanket ROCm test skips and fix FP8 hardware capability gates to support AMD MI300/MI350 GPUs alongside NVIDIA SM89+/SM90+. test/float8/test_fsdp2/test_fsdp2.py: - Replace dual module-level skip (is_sm_at_least_89 + ROCm skip) with a single gate: is_sm_at_least_89() or is_MI300() or is_MI350() - Import e4m3_dtype from config and use it in test_amax_allreduce_device_mesh instead of hardcoded torch.float8_e4m3fn (MI300 uses float8_e4m3fnuz) test/dtypes/test_affine_quantized_tensor_parallel.py: - Remove module-level pytest.skip on ROCm that blocked all TP tests (Int8wo, Int4wo, Int8dq) even though they have no FP8 dependency - Fix Float8 TP class gate: use is_sm_at_least_90() instead of raw get_device_capability() >= (9, 0), which incorrectly passes on ROCm where gfx90a (MI250X) maps to (9, 0) despite lacking FP8 support Validated on MI250X (gfx90a, 8 GPUs): - FSDP2 Float8: correctly skipped (MI250X lacks FP8) - Affine quantized TP: 4 passed, 2 skipped (Int8wo 3/3, Int8dq 1/1) - Float8 TP classes correctly not defined on non-FP8 hardware * Fix ruff F401: remove unused pytest import in test_affine_quantized_tensor_parallel.py The pytest import was left over after removing the module-level pytest.skip on ROCm. * Fix ruff format: break long pytest.skip line
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andrewor14
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