Implement missing ISA feature flags for ARM64/Windows

[tonybaloney]

Most of the ARM64 feature flags aren't being enumerated in Windows.

I haven't found a solution for some advanced SME flags, although no commercial SoC exists for these and Windows doesn't support them yet anyway.

// TODO: There are no PF flags for these yet. 
// - sme_i16i32
// - sme_bi32i32

Also, SVE length is not available outside of the kernel register, so I've set a conservative value of the minimum supported (128 bits).

I tested this on two different ARM64 chipsets and compared it with the reported ISA features in Linux.

I've copied the Windows SDK values to the header incase the person compiling doesn't have the latest Windows SDK. Some of these values aren't documented.

The latest list of processor features is:

#define PF_FLOATING_POINT_PRECISION_ERRATA           0   
#define PF_FLOATING_POINT_EMULATED                   1   
#define PF_COMPARE_EXCHANGE_DOUBLE                   2   
#define PF_MMX_INSTRUCTIONS_AVAILABLE                3   
#define PF_PPC_MOVEMEM_64BIT_OK                      4   
#define PF_ALPHA_BYTE_INSTRUCTIONS                   5   
#define PF_XMMI_INSTRUCTIONS_AVAILABLE               6   
#define PF_3DNOW_INSTRUCTIONS_AVAILABLE              7   
#define PF_RDTSC_INSTRUCTION_AVAILABLE               8   
#define PF_PAE_ENABLED                               9   
#define PF_XMMI64_INSTRUCTIONS_AVAILABLE            10   
#define PF_SSE_DAZ_MODE_AVAILABLE                   11   
#define PF_NX_ENABLED                               12   
#define PF_SSE3_INSTRUCTIONS_AVAILABLE              13   
#define PF_COMPARE_EXCHANGE128                      14   
#define PF_COMPARE64_EXCHANGE128                    15   
#define PF_CHANNELS_ENABLED                         16   
#define PF_XSAVE_ENABLED                            17   
#define PF_ARM_VFP_32_REGISTERS_AVAILABLE           18   
#define PF_ARM_NEON_INSTRUCTIONS_AVAILABLE          19   
#define PF_SECOND_LEVEL_ADDRESS_TRANSLATION         20   
#define PF_VIRT_FIRMWARE_ENABLED                    21   
#define PF_RDWRFSGSBASE_AVAILABLE                   22   
#define PF_FASTFAIL_AVAILABLE                       23   
#define PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE         24   
#define PF_ARM_64BIT_LOADSTORE_ATOMIC               25   
#define PF_ARM_EXTERNAL_CACHE_AVAILABLE             26   
#define PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE          27   
#define PF_RDRAND_INSTRUCTION_AVAILABLE             28   
#define PF_ARM_V8_INSTRUCTIONS_AVAILABLE            29   
#define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE     30   
#define PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE      31   
#define PF_RDTSCP_INSTRUCTION_AVAILABLE             32   
#define PF_RDPID_INSTRUCTION_AVAILABLE              33   
#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE    34   
#define PF_MONITORX_INSTRUCTION_AVAILABLE           35   
#define PF_SSSE3_INSTRUCTIONS_AVAILABLE             36   
#define PF_SSE4_1_INSTRUCTIONS_AVAILABLE            37   
#define PF_SSE4_2_INSTRUCTIONS_AVAILABLE            38   
#define PF_AVX_INSTRUCTIONS_AVAILABLE               39   
#define PF_AVX2_INSTRUCTIONS_AVAILABLE              40   
#define PF_AVX512F_INSTRUCTIONS_AVAILABLE           41   
#define PF_ERMS_AVAILABLE                           42   
#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE        43   
#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE     44   
#define PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE     45   
#define PF_ARM_SVE_INSTRUCTIONS_AVAILABLE           46   
#define PF_ARM_SVE2_INSTRUCTIONS_AVAILABLE          47   
#define PF_ARM_SVE2_1_INSTRUCTIONS_AVAILABLE        48   
#define PF_ARM_SVE_AES_INSTRUCTIONS_AVAILABLE       49   
#define PF_ARM_SVE_PMULL128_INSTRUCTIONS_AVAILABLE  50   
#define PF_ARM_SVE_BITPERM_INSTRUCTIONS_AVAILABLE   51   
#define PF_ARM_SVE_BF16_INSTRUCTIONS_AVAILABLE      52   
#define PF_ARM_SVE_EBF16_INSTRUCTIONS_AVAILABLE     53   
#define PF_ARM_SVE_B16B16_INSTRUCTIONS_AVAILABLE    54   
#define PF_ARM_SVE_SHA3_INSTRUCTIONS_AVAILABLE      55   
#define PF_ARM_SVE_SM4_INSTRUCTIONS_AVAILABLE       56   
#define PF_ARM_SVE_I8MM_INSTRUCTIONS_AVAILABLE      57   
#define PF_ARM_SVE_F32MM_INSTRUCTIONS_AVAILABLE     58   
#define PF_ARM_SVE_F64MM_INSTRUCTIONS_AVAILABLE     59   
#define PF_BMI2_INSTRUCTIONS_AVAILABLE              60   
#define PF_MOVDIR64B_INSTRUCTION_AVAILABLE          61   
#define PF_ARM_LSE2_AVAILABLE                       62   
#define PF_RESERVED_FEATURE                         63   
#define PF_ARM_SHA3_INSTRUCTIONS_AVAILABLE          64   
#define PF_ARM_SHA512_INSTRUCTIONS_AVAILABLE        65   
#define PF_ARM_V82_I8MM_INSTRUCTIONS_AVAILABLE      66   
#define PF_ARM_V82_FP16_INSTRUCTIONS_AVAILABLE      67   
#define PF_ARM_V86_BF16_INSTRUCTIONS_AVAILABLE      68   
#define PF_ARM_V86_EBF16_INSTRUCTIONS_AVAILABLE     69   
#define PF_ARM_SME_INSTRUCTIONS_AVAILABLE           70   
#define PF_ARM_SME2_INSTRUCTIONS_AVAILABLE          71   
#define PF_ARM_SME2_1_INSTRUCTIONS_AVAILABLE        72   
#define PF_ARM_SME2_2_INSTRUCTIONS_AVAILABLE        73   
#define PF_ARM_SME_AES_INSTRUCTIONS_AVAILABLE       74   
#define PF_ARM_SME_SBITPERM_INSTRUCTIONS_AVAILABLE  75   
#define PF_ARM_SME_SF8MM4_INSTRUCTIONS_AVAILABLE    76   
#define PF_ARM_SME_SF8MM8_INSTRUCTIONS_AVAILABLE    77   
#define PF_ARM_SME_SF8DP2_INSTRUCTIONS_AVAILABLE    78   
#define PF_ARM_SME_SF8DP4_INSTRUCTIONS_AVAILABLE    79   
#define PF_ARM_SME_SF8FMA_INSTRUCTIONS_AVAILABLE    80   
#define PF_ARM_SME_F8F32_INSTRUCTIONS_AVAILABLE     81   
#define PF_ARM_SME_F8F16_INSTRUCTIONS_AVAILABLE     82   
#define PF_ARM_SME_F16F16_INSTRUCTIONS_AVAILABLE    83   
#define PF_ARM_SME_B16B16_INSTRUCTIONS_AVAILABLE    84   
#define PF_ARM_SME_F64F64_INSTRUCTIONS_AVAILABLE    85   
#define PF_ARM_SME_I16I64_INSTRUCTIONS_AVAILABLE    86   
#define PF_ARM_SME_LUTv2_INSTRUCTIONS_AVAILABLE     87   
#define PF_ARM_SME_FA64_INSTRUCTIONS_AVAILABLE      88   

[tonybaloney]

This switch statement did nothing so I removed it

[fbarchard]

generally looks good to me.

I'm able to compile for windows arm, but theres no easy way to test it without buying a qualcomm laptop?
Apple with arm, lets you run x86, so I gave it a shot on windows, but my x86 cant run arm .exe files.

I have a samsung s25 with basically the same cpu as windows qualcomm.
This is what it reports
cpu_info:
SoC name: Unknown
Microarchitectures:
8x Oryon
Cores:
0: 1 processor (0), Qualcomm Oryon
1: 1 processor (1), Qualcomm Oryon
2: 1 processor (2), Qualcomm Oryon
3: 1 processor (3), Qualcomm Oryon
4: 1 processor (4), Qualcomm Oryon
5: 1 processor (5), Qualcomm Oryon
6: 1 processor (6), Qualcomm Oryon
7: 1 processor (7), Qualcomm Oryon
Clusters:
0: 2 processors (0-1), 0: 2 cores (0-1), Qualcomm Oryon
1: 6 processors (2-7), 1: 6 cores (2-7), Qualcomm Oryon
Logical processors (System ID):
0 (6)
1 (7)
2 (0)
3 (1)
4 (2)
5 (3)
6 (4)
7 (5)

isa_info:
Instruction sets:
ARM v8.1 atomics: yes
ARM v8.1 SQRDMLxH: yes
ARM v8.2 FP16 arithmetics: yes
ARM v8.2 FHM: yes
ARM v8.2 BF16: yes
ARM v8.2 Int8 dot product: yes
ARM v8.2 Int8 matrix multiplication: yes
ARM v8.3 JS conversion: yes
ARM v8.3 complex: yes
SIMD extensions:
ARM SVE: no
ARM SVE 2: no
ARM SME: no
ARM SME 2: no
ARM SVE Capabilities:
SVE max length: 0
SME max length: 0
Cryptography extensions:
AES: yes
SHA1: yes
SHA2: yes
PMULL: yes
CRC32: yes

and it has linux style cpuinfo
more /proc/cpuinfo
::::::::::::::
/proc/cpuinfo
::::::::::::::
processor : 0
BogoMIPS : 38.40
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 sm4 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 rng bti ecv afp rpres
CPU implementer : 0x51
CPU architecture: 8
CPU variant : 0x4
CPU part : 0x001
CPU revision : 4

The vendor/SoC name is really qualcomm and should probably report
adb shell getprop "ro.soc.model"
SM8750

The device
adb shell getprop "ro.product.bootimage.model"
SM-S936U
The device is [ro.product.brand]: [samsung]
But the SoC is really qualcomm, with qualcomm specific (Oryon) cores.

It would be good to have feature parity with android here. A nearly exact same SOC will appear in both Windows and Android devices.
The next Oryon gen3 has SME1.
The Lumix C1 is out for Android devices and has SME2p3 and SVE2p1, with many of those ISA.
But each vendor (e.g. samsung, qualcomm, apple, google) can implement a subset of lumix isa.

[tonybaloney]

You can test it on the windows-11-arm runner on GitHub actions. That's the only option if you don't have the laptop.

I've tested this on 2 different Windows on ARM64 laptops, one is the Qualcomm Snapdragon X Elite and it's identifying the correct features. That particular SoC doesn't have SVE or SME.
I tested a SoC that has SVE and SVE2, both were detected correctly.

I've discussed this patch with some engineers at ARM (I work for Microsoft btw) to verify the particular flags. The cpuinfo_isa.svelen gap is something I'll have to raise in another PR once I follow up with the kernel engineers to get this in the SDK