Glossary

insn

Abbreviation for "instruction".

INTA

Maskable interrupt acknowledge.

IRD

Interrupt response data/vector, the 8-bit value read by the CPU from de data bus during an INTA M-cycle.

ISR

Interrupt service routine.

M-cycle

Machine cycle.

MLAST

The last M-cycle of an instruction.

NMIA

Non-maskable interrupt acknowledge.

T-state

A CPU clock cycle.

TLAST

The last T-state of an instruction.

VZ80R

Visual Z80 Remix, an electronic simulator of the Zilog Z80.