ast2600: Add core boot peripherals (SCU, SDMC, WDT, Timer, FMC)#190
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garybeihl wants to merge 4 commits intorenode:masterfrom
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ast2600: Add core boot peripherals (SCU, SDMC, WDT, Timer, FMC)#190garybeihl wants to merge 4 commits intorenode:masterfrom
garybeihl wants to merge 4 commits intorenode:masterfrom
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System Control Unit model matching QEMU ast2600_a3_resets[] register layout. Implements all registers needed for u-boot SPL and Linux clk-ast2600 driver: - Protection Key unlock (0x1688A8A8) - Silicon Revision (0x05030303 for A3) - 5 PLL pairs (HPLL/APLL/MPLL/EPLL/DPLL) with lock bit (bit 31) - Clock Stop/Source Selection registers (0x080-0x350) - Hardware Strap 1 (0x500) and 2 (0x510) - Pin Control registers (0x400-0x4FC) - CPU scratch pad registers (0x180-0x1CC) - MiscCtrl (0x0C0) with UART_DIV13_EN - Reset Control, Debug Control, Chip ID, RNG - Fallback R/W storage for unnamed registers Signed-off-by: Gary Beihl <garybeihl@microsoft.com>
SDRAM Memory Controller model matching QEMU aspeed_sdmc.c behavior: - Protection key with QEMU-style transform: unlock (0xFC600309) sets 0x01, hardlock (0xDEADDEAD) sets 0x10, else 0x00 - Memory configuration register (1 GiB DRAM encoding) - Status1 (0x60): always set PHY_PLL_LOCK, clear BUSY - ECC Test Ctrl (0x70): always set FINISHED, clear FAIL - Config (0x04): preserves read-only HW config bits on write - Full 0x000-0xFFF register file with R/W storage - PHY registers at 0x400+ initialized with passing defaults u-boot SPL reads MCR04 for DRAM size and boots through full DDR training sequence. Signed-off-by: Gary Beihl <garybeihl@microsoft.com>
Aspeed_WDT: Watchdog Timer (4 instances on AST2600). Supports counter status/reload, restart magic (0x4755), control with AST2600-specific sanitization, reset width with polarity magic. Aspeed_Timer: 8-channel down-counting timer with shared CTRL register (4 bits/timer), IRQ status (W1C), match registers. Implements INumberedGPIOOutput for GIC wiring. Signed-off-by: Gary Beihl <garybeihl@microsoft.com>
Firmware Memory Controller with dual ConnectionRegion registration: - "registers" at 0x1E620000 for MMIO control - "flash" at 0x20000000 for memory-mapped flash window Flash window supports two modes via CE0 Control Register: - Normal mode (type=0): reads/writes pass through to MappedMemory - User mode (type=3): SPI commands routed to GenericSpiFlash User mode enables Linux spi-aspeed-smc driver to send JEDEC Read ID (0x9F). Flash configured as Winbond W25Q512JV (0xEF/0x40/0x20), recognized by kernel spi-nor driver for MTD partitions. Also includes: - DMA engine with grant handshake (0xAEED0000/0xDEEA0000 magic) - DMA flash-to-DRAM copy and checksum accumulation - CE0-CE2 control registers with SPI mode and clock config - Timing calibration with HCLK divisor table - DMA completion interrupt support Signed-off-by: Gary Beihl <garybeihl@microsoft.com>
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Summary
Add the boot-critical peripheral models for the Aspeed AST2600 SoC, enabling u-boot SPL through full Linux kernel boot:
Boot sequence enabled
Developed and tested against OpenBMC evb-ast2600 firmware image.
Test plan