9Bit-Pipelined-CPU

A Pipelined 9-Bit CPU Simulation in System Verilog.

This was a project completed for CSE 141L Computer Architecture Project at UCSD
Taught by Dean Tullsen in Fall 2013

The project consisted of incrementally developing a CPU in stages:
1. Design an ISA and Write 3 Programs (Pattern Counter, Multiplier, Occurrence Counter).
2. Design ALU, Program Counter, Register File.
3. Connect the modules of your design to construct a fully fledged single cycle Processor (optimize for cycle count).
4. Turn your CPU into a pipelined architecture.

Inside each stage of CPU development, there's a DOCS folder which details the ISA, CPU design specs, and the programs written for it.