Expand description of registers and their uses#76
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scotws wants to merge 3 commits intoriscv-non-isa:mainfrom
Open
Expand description of registers and their uses#76scotws wants to merge 3 commits intoriscv-non-isa:mainfrom
scotws wants to merge 3 commits intoriscv-non-isa:mainfrom
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aswaterman
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Feb 28, 2022
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Generally LGTM, @aswaterman do you mind having a final review for that? |
aswaterman
reviewed
Apr 1, 2022
| processors such as the ARM-32. The first register, `x0`, has a special function: | ||
| Reading it always returns 0 and writes to it are ignored. As we will see later, | ||
| this allows various tricks and simplifications. | ||
| The **instruction set architecture** (ISA) of RISC-V contains 32 registers. |
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The old wording was more precise. It's a true statement that the RV32I and RV64I base ISAs contain 32 registers. But the other base ISA (RV32E) has only 16 registers, and various ISA extensions (like F) increase the register count beyond 32.
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Distinguish between the
x-register view and the ABI used by the programmer; include "RV32E" as reason for strange distribution of register ABI. Minor formatting changes.