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vasu-rivosinc merged 6 commits into from
Feb 10, 2026
Merged

Arc review changes #11

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458984c
Updated content to incorporate feedback from ARC review
vasu-rivosinc Feb 3, 2026
6d532b5
More changes to fix formatting
vasu-rivosinc Feb 4, 2026
8ffad3c
Fixed spelling errors
vasu-rivosinc Feb 4, 2026
b346f9c
more feedback changes
vasu-rivosinc Feb 9, 2026
5853968
- Restructured Chapter 3 to split examples into individual adoc files.
vasu-rivosinc Feb 10, 2026
f80f385
Updated version to 0.9.1
vasu-rivosinc Feb 10, 2026
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3 changes: 3 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -5,6 +5,9 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).

## [0.9.1]
- Updated content to incorporate feedback from the Arch Review.

## [0.9.0]
- Updated to 0.9.0 for Arch Review and Freeze.

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2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -16,7 +16,7 @@ DOCS := \
riscv-rqsc.adoc

DATE ?= $(shell date +%Y-%m-%d)
VERSION ?= v0.9.0
VERSION ?= v0.9.1
REVMARK ?= Draft
DOCKER_IMG := riscvintl/riscv-docs-base-container-image:latest
ifneq ($(SKIP_DOCKER),true)
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300 changes: 195 additions & 105 deletions src/chapter2.adoc
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14 changes: 7 additions & 7 deletions src/chapter3-ex1.adoc
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Expand Up @@ -38,7 +38,7 @@ Cluster 1 L2 cache is shared by 4 cores labeled Core 4 to 7.
Shared LLC (e.g. L3) is shared by all 8 cores.
Shared LLC is connected to 3 memory controllers labeled 0 to 2. Each Memory Controller
has 1 DDR Channel. The DDR Memory is configured in UMA mode with same
proxmity domain for all memory channels.
proximity domain for all memory channels.

The system implements the following Capacity and Memory Bandwidth QoS controllers.

Expand Down Expand Up @@ -77,7 +77,7 @@ Name(\RQSC, Package()
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (QWORD)
0x04, // Access Size (DWORD)
0x0000000004821000, // Address
},
64, // RCID Count
Expand All @@ -103,7 +103,7 @@ Name(\RQSC, Package()
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (QWORD)
0x04, // Access Size (DWORD)
0x0000000004822000, // Address
},
64, // RCID Count
Expand All @@ -129,7 +129,7 @@ Name(\RQSC, Package()
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (QWORD)
0x04, // Access Size (DWORD)
0x0000000004823000, // Address
},
64, // RCID Count
Expand All @@ -155,7 +155,7 @@ Name(\RQSC, Package()
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (QWORD)
0x04, // Access Size (DWORD)
0x0000000004828000, // Address
},
64, // RCID Count
Expand All @@ -181,7 +181,7 @@ Name(\RQSC, Package()
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (QWORD)
0x04, // Access Size (DWORD)
0x0000000004829000, // Address
},
64, // RCID Count
Expand All @@ -207,7 +207,7 @@ Name(\RQSC, Package()
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (QWORD)
0x04, // Access Size (DWORD)
0x000000000482A000, // Address
},
64, // RCID Count
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259 changes: 259 additions & 0 deletions src/chapter3-ex2.adoc
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@@ -0,0 +1,259 @@
=== Example 2: Single Socket System with 8 cores and 4 memory controllers with NUMA enabled

The diagram below shows a model of the SoC described in this example.

.Single Socket System Example 2
[[EXAMPLE2_FIGURE]]
[ditaa, "single-socket-system-example-2"]
----

+------------+ +------------+ +------------+ +------------+ +------------+ +------------+ +------------+ +------------+
| | | | | | | | | | | | | | | |
| Core 0 | | Core 1 | | Core 2 | | Core 3 | | Core 4 | | Core 5 | | Core 6 | | Core 7 |
| | | | | | | | | | | | | | | |
+------------+ +------------+ +------------+ +------------+ +------------+ +------------+ +------------+ +------------+

+------------------------------------------------------------+ +------------------------------------------------------------+
| | | |
| Cluster 0 L2 Cache (Shared by C0 to C3) | | Cluster 1 L2 Cache (Shared by C4 to C7) |
| | | |
+------------------------------------------------------------+ +------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------+
| |
| Shared LLC (Shared by 8 Cores) |
| |
+------------------------------------------------------------------------------------------------------------------------------+

+---------------------------+ +---------------------------+ +---------------------------+ +---------------------------+
| | | | | | | |
| Memory Controller 0 | | Memory Controller 1 | | Memory Controller 2 | | Memory Controller 3 |
| | | | | | | |
+---------------------------+ +---------------------------+ +---------------------------+ +---------------------------+

----

In the example system above, cluster 0 L2 cache is shared by 4 cores labeled Core 0 to 3.
Cluster 1 L2 cache is shared by 4 cores labeled Core 4 to 7.
Shared LLC (e.g. L3) is shared by all 8 cores.
Shared LLC is connected to 4 memory controllers labeled 0 to 3. Each Memory Controller
has 1 DDR Channel. The DDR Memory is configured in NUMA mode with 2 proximity domains
where memory controllers 0 and 1 serve cores 0 to 3 and memory controllers
2 and 3 serve cores 4 to 7.

When configuring the QoS parameters for the memory QoS controllers, QoS controllers of
memory controllers 0 and 1 must be configured with the same parameters and QoS controllers of
memory controllers 2 and 3 must be configured with the same parameters.

The system implements the following Capacity and Memory Bandwidth QoS controllers.

* 2 L2 Cache Capacity QoS Controllers (one per cluster)
** CBQRI located at `0x04821000` and `0x04822000`
* 1 LLC Cache Capacity QoS Controller
** CBQRI located at `0x04823000`
* 4 Memory Bandwidth QoS Controllers (one per memory controller)
** CBQRI located at `0x04828000`, `0x04829000`, `0x0482A000` and `0x0482B000`

Globally all of the QoS Controllers implement 64 RCIDs and 256 MCIDs.

==== RQSC Table

[source, c]
----
Name(\RQSC, Package()
{
"RQSC", // Signature
0x000000FF, // Total Length of RQSC Table (to be fixed)
0x01, // Revision
0xFF, // Checksum (to be fixed)
"RIVOS ", // OEMID
"RVOS ", // OEM Table ID
0x00000001, // OEM Revision
"RVOS", // Creator ID
0x00000001, // Creator Revision
0x00000006, // Number of QoS Controllers
Package() // QoS Controller 1 - Cluster 0 L2 Cache Capacity QoS Controller
{
0x00, // Controller Type - Capacity
0x00, // Reserved
0xFFFF, // Length (to be fixed)
Package() // Register Interface Address
{
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (DWORD)
0x0000000004821000, // Address
},
64, // RCID Count
256, // MCID Count
0x0000, // Controller Flags
0x0001, // Number of Resources
Package() // Resource Structure - Cluster 0 L2 Cache
{
0x00, // Resource Type (Cache)
0x0F, // Length (16 bytes)
0x0000, // Resource Flags
0x0000000000000000, // Resource ID 1 (Cache ID from PPTT)
0x00000000, // Resource ID 2 (0)
},
},
Package() // QoS Controller 2 - Cluster 1 L2 Cache Capacity QoS Controller
{
0x00, // Controller Type - Capacity
0x00, // Reserved
0xFFFF, // Length (to be fixed)
Package() // Register Interface Address
{
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (DWORD)
0x0000000004822000, // Address
},
64, // RCID Count
256, // MCID Count
0x0000, // Controller Flags
0x0001, // Number of Resources
Package() // Resource Structure - Cluster 1 L2 Cache
{
0x00, // Resource Type (Cache)
0x0F, // Length (16 bytes)
0x0000, // Resource Flags
0x0000000000000001, // Resource ID 1 (Cache ID from PPTT)
0x00000000, // Resource ID 2 (0)
},
},
Package() // QoS Controller 3 - Shared LLC Cache Capacity QoS Controller
{
0x00, // Controller Type - Capacity
0x00, // Reserved
0xFFFF, // Length (to be fixed)
Package() // Register Interface Address
{
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (DWORD)
0x0000000004823000, // Address
},
64, // RCID Count
256, // MCID Count
0x0000, // Controller Flags
0x0001, // Number of Resources
Package() // Resource Structure - Shared LLC Cache
{
0x00, // Resource Type (Cache)
0x0F, // Length (16 bytes)
0x0000, // Resource Flags
0x0000000000000002, // Resource ID 1 (Cache ID from PPTT)
0x00000000, // Resource ID 2 (0)
},
},
Package() // QoS Controller 4 - Memory Controller 0 Bandwidth QoS Controller
{
0x01, // Controller Type - Bandwidth
0x00, // Reserved
0xFFFF, // Length (to be fixed)
Package() // Register Interface Address
{
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (DWORD)
0x0000000004828000, // Address
},
64, // RCID Count
256, // MCID Count
0x0000, // Controller Flags
0x0001, // Number of Resources
Package() // Resource Structure - Proximity Domain
{
0x01, // Resource Type (Memory)
0x0F, // Length (16 bytes)
0x0000, // Resource Flags
0x0000000000000000, // Resource ID 1 (Proximity Domain from SRAT table for this memory)
0x00000000, // Resource ID 2 (0)
},
},
Package() // QoS Controller 5 - Memory Controller 1 Bandwidth QoS Controller
{
0x01, // Controller Type - Bandwidth
0x00, // Reserved
0xFFFF, // Length (to be fixed)
Package() // Register Interface Address
{
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (DWORD)
0x0000000004829000, // Address
},
64, // RCID Count
256, // MCID Count
0x0000, // Controller Flags
0x0001, // Number of Resources
Package() // Resource Structure - Proximity Domain
{
0x01, // Resource Type (Memory)
0x0F, // Length (16 bytes)
0x0000, // Resource Flags
0x0000000000000000, // Resource ID 1 (Proximity Domain from SRAT table for this memory)
0x00000000, // Resource ID 2 (0)
},
},
Package() // QoS Controller 6 - Memory Controller 2 Bandwidth QoS Controller
{
0x01, // Controller Type - Bandwidth
0x00, // Reserved
0xFFFF, // Length (to be fixed)
Package() // Register Interface Address
{
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (DWORD)
0x000000000482A000, // Address
},
64, // RCID Count
256, // MCID Count
0x0000, // Controller Flags
0x0001, // Number of Resources
Package() // Resource Structure - Proximity Domain
{
0x01, // Resource Type (Memory)
0x0F, // Length (16 bytes)
0x0000, // Resource Flags
0x0000000000000001, // Resource ID 1 (Proximity Domain from SRAT table for this memory)
0x00000000, // Resource ID 2 (0)
},
},
Package() // QoS Controller 7 - Memory Controller 3 Bandwidth QoS Controller
{
0x01, // Controller Type - Bandwidth
0x00, // Reserved
0xFFFF, // Length (to be fixed)
Package() // Register Interface Address
{
0x00, // System Memory Space
0x00, // Size of Register in bits (0)
0x00, // Register Offset (0)
0x04, // Access Size (DWORD)
0x000000000482B000, // Address
},
64, // RCID Count
256, // MCID Count
0x0000, // Controller Flags
0x0001, // Number of Resources
Package() // Resource Structure - Proximity Domain
{
0x01, // Resource Type (Memory)
0x0F, // Length (16 bytes)
0x0000, // Resource Flags
0x0000000000000001, // Resource ID 1 (Proximity Domain from SRAT table for this memory)
0x00000000, // Resource ID 2 (0)
},
},

})
----
1 change: 1 addition & 0 deletions src/chapter3.adoc
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Expand Up @@ -4,3 +4,4 @@
This chapter covers some system implementation examples.

include::chapter3-ex1.adoc[]
include::chapter3-ex2.adoc[]
2 changes: 1 addition & 1 deletion src/riscv-rqsc.adoc
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Expand Up @@ -3,7 +3,7 @@
:description: RISC-V Quality of Service Controllers Table (RQSC) ACPI Specification
:company: RISC-V.org
:revdate: 9/2025
:revnumber: 0.9
:revnumber: 0.9.1
:revremark: Draft
:revinfo:
:url-riscv: http://riscv.org
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