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riscv-software-src / riscv-isa-sim Public

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Debug Quick Test

Fix VS-mode check for sireg* (really vsireg*) CSRs #1728

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Fix VS-mode check for sireg* (really vsireg*) CSRs

Fix VS-mode check for sireg* (really vsireg*) CSRs #1728

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Summary
Jobs
- Test debug (Ubuntu)
Run details
- Usage
- Workflow file

Usage Workflow file

Test debug (Ubuntu)

succeeded Nov 29, 2025 in 16m 37s

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