Zvkg Test Generation and Covergroup Generation#1596
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David Harris (davidharrishmc) merged 20 commits intoJun 1, 2026
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Signed-off-by: Ryan Wolk <rwolk@hmc.edu> Co-authored-by: Claude
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
cr_vl_lmul_egs4_sew32 is still a work in progress Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
The main changes involve better handling of cases where things are weird because vl is four instead of one. This means that we need to read potentially four registers for edge detection, and the vl crosses get a lot more complicated due to the limitations placed on vl in by the egs. Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
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Coverage is now fully working, so this is ready for a review. |
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Pull request overview
Adds Zvkg vector-crypto test generation and coverage scaffolding for vghsh.vv and vgmul.vv, including EGS=4-aware helpers in the test generator and SystemVerilog covergroup templates, plus framework helpers (get_vr_val_lmul4, vs_edges_check_sew32_egs4, vl_check(egs)). Tests assemble/run on simulators; coverage is generated but not yet expected to hit (a known WIP for cr_vl_lmul_egs4_sew32).
Changes:
- New
testplans/Zvkg.csvand supporting_egs4dispatches invector-testgen-unpriv.py/vector_testgen_common.py, including crypto instruction classification, EGS-aware register/VL/edge generators, EGS-aware signature update, and 128-bit edge data emission. - New EGS4 coverage templates (
cp_v{d,s1,s2}_egs4,*_edges_egs4,cmp_*_egs4,cr_vs2_vs1/vd/vs1_vd_edges_egs4,cr_vl_lmul_egs4_sew32,cr_vtype_agnostic_egs4,cp_masking_edges_egs4) plus generatedZvkg_coverage.svh/_init.svhand wiring in base sample/init/config. - Framework helpers:
get_vr_val_lmul4,vs_edges_check_sew32_egs4,vl_check(egs), and_get_effew("Zvk*") → 32.
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Copilot reviewed 6 out of 29 changed files in this pull request and generated 1 comment.
Show a summary per file
| File | Description |
|---|---|
| testplans/Zvkg.csv | New testplan defining vghsh.vv and vgmul.vv with EGS4 coverpoints. |
| testplans/Zvk.tmpcsv | WIP planning notes for vector crypto extensions. |
| generators/testgen/scripts/vector-testgen-unpriv.py | EGS4-aware make_* helpers, dispatches, SEW=32 for /Zvkg path. |
| generators/testgen/scripts/vector_testgen_common.py | Crypto instruction classification, EGS-aware writeTest/SIGUPD, 128-bit edge data, prepBaseV EGS handling. |
| generators/coverage/src/covergroupgen/generate.py | Maps Zvk* (non-Zvkb) to EFFEW32. |
| generators/coverage/src/covergroupgen/templates/vector/*_egs4.sv | New EGS4 coverpoint/cross templates. |
| framework/src/act/fcov/coverage/RISCV_instruction_base.svh | Adds get_vr_val_lmul4. |
| framework/src/act/fcov/coverage/RISCV_coverage_vector.svh | Adds vs_edges_check_sew32_egs4 and vl_check EGS argument. |
| coverpoints/unpriv/Zvkg_coverage*.svh | Generated Zvkg covergroup and init. |
| coverpoints/coverage/RISCV_*.svh | Wires Zvkg into sample/init/config and decode. |
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
David Harris (davidharrishmc)
requested changes
May 30, 2026
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
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David Harris (davidharrishmc)
approved these changes
Jun 1, 2026
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
Signed-off-by: Ryan Wolk <rwolk@hmc.edu>
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This patch adds test generation for basic egs = 4 instructions from the Zvkg extension. These tests generate and run on all simulators, but do not collect any coverage as of now. Coverage seems like it will turn out to be a bigger problem to solve as many of the utilities assume that vl = 1 to collect coverage. Each test in this suite requires vl = 4, with edge values that can potentially span multiple vector registers which something like vs_edges_check is not built for, so it will take some effort to bring up coverage for the edges coverpoints. As of now, this means that coverage is at 0% because it throws an error. The covergroup template for cr_vl_lmul_edg4_sew32 is also a work in progress.