Add Sspmp extension

src/images/bytefield/mpmpdeleg_format_rv64.edn

@@ -0,0 +1,14 @@
+[bytefield]
+----
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 20}])
+(def row-height 30)
+(def row-header-fn nil)
+(def boxes-per-row 32)
+(draw-column-headers {:height 20 :font-size 20 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "6" "" "7" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
+
+(draw-box (text "Reserved (WPRI)" {:font-size 22}) {:span 18})
+(draw-box (text "pmpnum (WARL)" {:font-size 22}) {:span 14})
+
+(draw-box (text "MXLEN-7" {:font-size 20}) {:span 18 :borders {}})
+(draw-box (text "7" {:font-size 20}) {:span 14 :borders {}})
+----

src/images/bytefield/spmpaddr-rv32.edn

@@ -0,0 +1,15 @@
+[bytefield]
+----
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
+(def left-margin 30)
+(def right-margin 30)
+(def row-height 40)
+(def row-header-fn nil)
+(def boxes-per-row 32)
+(draw-column-headers {:height 30 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" ""  "" "" "" "" "" "" "" "" "" "" "" "" "" "" "31"])})
+
+(draw-box "address[33:2]" {:span 16 :text-anchor "end" :borders {:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "(WARL)" {:span 16 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
+
+(draw-box "32" {:span 32 :borders {}})
+----

src/images/bytefield/spmpaddr-rv64.edn

@@ -0,0 +1,17 @@
+[bytefield]
+----
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
+(def left-margin 30)
+(def right-margin 30)
+(def row-height 40)
+(def row-header-fn nil)
+(def boxes-per-row 32)
+(draw-column-headers {:height 30 :font-size 24 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "53" "54" "" "" "" "" "" "" "63"])})
+
+(draw-box "0" {:span 8})
+(draw-box "address[55:2]" {:span 12 :text-anchor "end" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "(WARL)" {:span 12 :text-anchor "start" :borders{:top :border-unrelated :bottom :border-unrelated :right :border-unrelated}})
+
+(draw-box "10" {:font-size 24 :span 8 :borders {}})
+(draw-box "54" {:font-size 24 :span 24 :borders {}})
+----

src/images/bytefield/spmpcfg.edn

@@ -0,0 +1,45 @@
+[bytefield]
+----
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 20}])
+(def left-margin 30)
+(def right-margin 30)
+(def row-height 40)
+(def row-header-fn nil)
+(def boxes-per-row 44)
+
+
+(draw-box "SXLEN-1" {:span 4 :text-anchor "start" :borders {}})
+(draw-box "10" {:span 4 :text-anchor "end" :borders {}})
+(draw-box "9" {:span 4 :borders {}})
+(draw-box "8" {:span 4 :borders {}})
+(draw-box "7" {:span 4 :borders {}})
+(draw-box "6" {:span 3 :text-anchor "start" :borders {}})
+(draw-box "5" {:span 3 :text-anchor "end" :borders {}})
+(draw-box "4" {:span 3 :text-anchor "start" :borders {}})
+(draw-box "3" {:span 3 :text-anchor "end" :borders {}})
+(draw-box "2" {:span 4 :borders {}})
+(draw-box "1" {:span 4 :borders {}})
+(draw-box "0" {:span 4 :borders {}})
+
+
+(draw-box "Reserved (WPRI)" {:span 8 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "SHARED (WARL)" {:span 4 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "U (WARL)" {:span 4 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "L (WARL)" {:span 4 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "Reserved (WPRI)" {:span 6 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "A (WARL)" {:span 6 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "X (WARL)" {:span 4 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "W (WARL)" {:span 4 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated}})
+(draw-box "R (WARL)" {:span 4 :text-anchor "middle" :borders{:top :border-unrelated :bottom :border-unrelated :left :border-unrelated :right :border-unrelated}})
+
+
+(draw-box "SXLEN-10" {:span 8 :borders {}})
+(draw-box "1" {:span 4 :borders {}})
+(draw-box "1" {:span 4 :borders {}})
+(draw-box "1" {:span 4 :borders {}})
+(draw-box "2" {:span 6 :borders {}})
+(draw-box "2" {:span 6 :borders {}})
+(draw-box "1" {:span 4 :borders {}})
+(draw-box "1" {:span 4 :borders {}})
+(draw-box "1" {:span 4 :borders {}})
+----

src/machine.adoc

@@ -625,6 +625,7 @@ The implementation choice is observable only by privilege modes with an XLEN
 setting greater than the current XLEN; it is invisible to the current
 privilege mode.
 
+[[mstatus-memory-privilege]]
 ===== Memory Privilege in `mstatus` Register
 
 The MPRV (Modify PRiVilege) bit modifies the _effective privilege mode_,
@@ -3416,6 +3417,7 @@ store-conditional, AMO, or cache-block zero instruction which accesses a physica
 within a PMP region without write permissions raises a store
 access-fault exception.
 
+[[pmp-address-matching]]
 ===== Address Matching
 
 The A field in a PMP entry's configuration register encodes the

src/priv-csrs.adoc

@@ -359,6 +359,8 @@ Supervisor indirect register alias 6.
 4+^|Supervisor Protection and Translation
 
 |`0x180` |SRW |`satp` |Supervisor address translation and protection.
+|`0x183` |SRW |`spmpen` |Supervisor physical memory protection mask.
+|`0x193` |SRW |`spmpenh` |Upper 32 bits of supervisor physical memory protection mask, RV32 only.
 
 4+^|Supervisor Timer Compare
 
@@ -782,19 +784,23 @@ Machine indirect register alias 6.
 |`0x30A` +
 `0x31A` +
 `0x747` +
-`0x757`
+`0x757` +
+`0x316` +
 |MRW +
 MRW +
 MRW +
+MRW +
 MRW
 |`menvcfg` +
 `menvcfgh` +
 `mseccfg` +
-`mseccfgh`
+`mseccfgh` +
+`mpmpdeleg`
 |Machine environment configuration register. +
 Upper 32 bits of `menvcfg`, RV32 only. +
 Machine security configuration register. +
-Upper 32 bits of `mseccfg`, RV32 only.
+Upper 32 bits of `mseccfg`, RV32 only. +
+Physical memory protection delegation register.
 
 4+^|Machine Memory Protection