Draft of Smpmpind, Smcfiss, Smucfiss, and Sspmpss extensions

[ved-rivos]

Draft specification for internal review

[aswaterman]

@ved-rivos RVIA instituted a requirement that commits be signed; see this guide.

github_signed_commits_step_by_step.pdf

[ved-rivos]

@aswaterman Thanks. I have signed the commit now.

[github-actions]

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Unprivileged Specification

================================================================================
Tag Changes Report
================================================================================

Reference file: ref/riscv-unprivileged-norm-tags.json
Current file: build/riscv-unprivileged-norm-tags.json
Added 309 tags:
  * "norm:Zabha_amocas-BH_ignore_bits": "The
AMOCAS.[B|H] instructions similarly ignore the image:../../build/images-out/stem-2aa35a881e52a66..."
  * "norm:Zabha_rd_sign_extension": "Byte and halfword AMOs always sign-extend the value placed in rd, and ignore
the image:../../build/i..."
  * "norm:Zabha_rs1_align_addr": "Similar to the AMOs specified in the A extension, the Zabha extension mandates
that the address cont..."
  * "norm:Zacas_amocas_mem_op_fail_aq_rl": "The memory operation performed by an
AMOCAS.W/D/Q, when not successful, has acquire semantics if aq ..."
  * "norm:Zacas_amocas_mem_op_success_aq_rl": "The memory operation performed by an
AMOCAS.W/D/Q, when successful, has acquire semantics if aq bit ..."
  * "norm:Zacas_amocas_rs1_addr_alignment": "AMOCAS.W/D/Q requires that the address
held in rs1 be naturally aligned to the size of the operand (..."
  * "norm:Zacas_amocas_w_permission": "An AMOCAS.W/D/Q instruction always requires write permissions."
  * "norm:Zacas_rv32_amocas-d_frst_pair_entry_reg_even": "The instruction requires the first register in
the pair to be even numbered; encodings with odd numb..."
  * "norm:Zacas_rv32_amocas-d_op": "For RV32, AMOCAS.D atomically loads 64-bits of a data value from address in
rs1, compares the loaded..."
  * "norm:Zacas_rv32_amocas-d_rd_frst_reg_x0": "When the first
register of a destination register pair is x0, then the entire register
result is dis..."
  * "norm:Zacas_rv32_amocas-d_rs2_frst_reg_x0": "When the first register of a source register
pair is x0, then both halves of the pair read as zero."
  * "norm:Zacas_rv32_amocas-w_op": "For RV32, AMOCAS.W atomically loads a 32-bit data value from address in rs1,
compares the loaded val..."
  * "norm:Zacas_rv64_amocas-d_op": "For RV64, AMOCAS.D atomically loads 64-bits of a data value from address in
rs1, compares the loaded..."
  * "norm:Zacas_rv64_amocas-q_frst_pair_entry_reg_even": "The instruction requires the first register in
the pair to be even numbered; encodings with odd numb..."
  * "norm:Zacas_rv64_amocas-q_op": "AMOCAS.Q (RV64 only) atomically loads 128-bits of a data value from address in
rs1, compares the loa..."
  * "norm:Zacas_rv64_amocas-q_rd_frst_reg_x0": "When the first register of a
destination register pair is x0, then the entire register result is dis..."
  * "norm:Zacas_rv64_amocas-q_rs2_frst_reg_x0": "When the first register of a source register pair
is x0, then both halves of the pair read as zero."
  * "norm:Zacas_rv64_amocas-w_op": "For RV64, AMOCAS.W atomically loads a 32-bit data value from address in
rs1, compares the loaded val..."
  * "norm:Zawrs_exec_resume_rules": "WRS.NTO and WRS.STO instructions follow the rules of the WFI instruction
for resuming execution on a..."
  * "norm:Zawrs_priv_illegal_instr_excp": "When the TW (Timeout Wait) bit in mstatus is set and WRS.NTO is executed
in any privilege mode other..."
  * "norm:Zawrs_stall_terminate": "While stalled, an implementation is permitted to occasionally terminate the
stall and complete execu..."
  * "norm:Zawrs_virtual_instr_excp": "When executing in VS or VU mode, if the VTW bit is set in hstatus, the
TW bit in mstatus is clear, a..."
  * "norm:Zawrs_wrs-nto_stall_exec": "Then a subsequent WRS.NTO instruction would cause the hart to temporarily
stall execution in a low-p..."
  * "norm:Zawrs_wrs-sto_stall_duration": "WRS.STO (WRS-with-short-timeout) is
provided that works like WRS.NTO but bounds the stall duration t..."
  * "norm:add_uw_enc": "Encoding"
  * "norm:add_uw_op": "Operation"
  * "norm:aes32dsi_enc": "Encoding"
  * "norm:aes32dsi_op": "Operation"
  * "norm:aes32dsmi_enc": "Encoding"
  * "norm:aes32dsmi_op": "Operation"
  * "norm:aes32esi_enc": "Encoding"
  * "norm:aes32esi_op": "Operation"
  * "norm:aes32esmi_enc": "Encoding"
  * "norm:aes32esmi_op": "Operation"
  * "norm:aes64ds_enc": "Encoding"
  * "norm:aes64ds_op": "Operation"
  * "norm:aes64dsm_enc": "Encoding"
  * "norm:aes64dsm_op": "Operation"
  * "norm:aes64es_enc": "Encoding"
  * "norm:aes64es_op": "Operation"
  * "norm:aes64esm_enc": "Encoding"
  * "norm:aes64esm_op": "Operation"
  * "norm:aes64im_enc": "Encoding"
  * "norm:aes64im_op": "Operation"
  * "norm:aes64ks1i_enc": "Encoding"
  * "norm:aes64ks1i_op": "Operation"
  * "norm:aes64ks2_enc": "Encoding"
  * "norm:aes64ks2_op": "Operation"
  * "norm:andn_enc": "Encoding"
  * "norm:andn_op": "Operation"
  * "norm:b_extension_composition": "The B standard extension comprises instructions provided by the Zba, Zbb, and
Zbs extensions."
  * "norm:base_integer_variants": "There are two primary base
integer variants, RV32I and RV64I, described in
<<rv32>> and ..."
  * "norm:bclr_enc": "Encoding"
  * "norm:bclr_op": "Operation"
  * "norm:bclri_op": "Operation"
  * "norm:bclri_rv32_enc": "Encoding (RV32)"
  * "norm:bclri_rv64_enc": "Encoding (RV64)"
  * "norm:bclri_shamt_rsv_rv32": "For RV32, the encodings corresponding to shamt[5]=1 are reserved."
  * "norm:bext_enc": "Encoding"
  * "norm:bext_op": "Operation"
  * "norm:bexti_op": "Operation"
  * "norm:bexti_rv32_enc": "Encoding (RV32)"
  * "norm:bexti_rv64_enc": "Encoding (RV64)"
  * "norm:bexti_shamt_rsv_rv32": "For RV32, the encodings corresponding to shamt[5]=1 are reserved."
  * "norm:binv_enc": "Encoding"
  * "norm:binv_op": "Operation"
  * "norm:binvi_op": "Operation"
  * "norm:binvi_rv32_enc": "Encoding (RV32)"
  * "norm:binvi_rv64_enc": "Encoding (RV64)"
  * "norm:binvi_shamt_rsv_rv32": "For RV32, the encodings corresponding to shamt[5]=1 are reserved."
  * "norm:bitmanip_bhw_suffix_semantics": "Bitmanip instructions with the suffixes .b, .h, and .w only look at the least-significant 8 bits, 16..."
  * "norm:bitmanip_rv32_rv64": "The bitmanip extensions are defined for RV32 and RV64."
  * "norm:bitmanip_uw_suffix_semantics": "Bitmanip instructions with the suffix .uw have one operand that is an unsigned 32-bit value that is ..."
  * "norm:bitmanip_w_suffix_semantics": "The bitmanip extension follows the convention in RV64 that w-suffixed instructions (without a dot be..."
  * "norm:brev8_enc": "Encoding"
  * "norm:brev8_op": "Operation"
  * "norm:bset_enc": "Encoding"
  * "norm:bset_op": "Operation"
  * "norm:bseti_op": "Operation"
  * "norm:bseti_rv32_enc": "Encoding (RV32)"
  * "norm:bseti_rv64_enc": "Encoding (RV64)"
  * "norm:bseti_shamt_rsv_rv32": "For RV32, the encodings corresponding to shamt[5]=1 are reserved."
  * "norm:clmul_enc": "Encoding"
  * "norm:clmul_op": "Operation"
  * "norm:clmulh_enc": "Encoding"
  * "norm:clmulh_op": "Operation"
  * "norm:clmulr_enc": "Encoding"
  * "norm:clmulr_op": "Operation"
  * "norm:clz_enc": "Encoding"
  * "norm:clz_op": "Operation"
  * "norm:clzw_enc": "Encoding"
  * "norm:clzw_op": "Operation"
  * "norm:cpop_enc": "Encoding"
  * "norm:cpop_op": "Operation"
  * "norm:cpopw_enc": "Encoding"
  * "norm:cpopw_op": "Operation"
  * "norm:ctz_enc": "Encoding"
  * "norm:ctz_op": "Operation"
  * "norm:ctzw_enc": "Encoding"
  * "norm:ctzw_op": "Operation"
  * "norm:execution_environment_implementation_flexibility": "The implementation of a RISC-V
execution environment can be pure hardware, pure software, or a
combi..."
  * "norm:f_depends_zicsr": "The F extension depends on the "Zicsr" extension for control and status register access."
  * "norm:f_ieee_compliance": "single-precision floating-point computational instructions compliant
with the IEEE 754-2008 arithmet..."
  * "norm:hpm_counter_op_sz_mode_dependency": "The Zihpm extension
depends on the Zicsr extension."
  * "norm:hpm_counter_op_sz_mode_xlen32": "When
XLEN=32, the upper 32 bits of these performance counters are accessible
via additional CSRs hpm..."
  * "norm:hpm_misconfigured_event_behavior": "If the configuration used to select the events
counted by a counter is misconfigured, the counter ma..."
  * "norm:hpm_platform_specific_impl": "The implemented number and width of these additional counters, and the
set of events they count, are..."
  * "norm:hpm_unimplemented_counter_access": "Accessing an
unimplemented counter may cause an illegal-instruction exception or may
return a consta..."
  * "norm:ldaq_aq_required": "This load must have the ordering annotation aq"
  * "norm:ldaq_atomic_load_enc": "Encoding"
  * "norm:ldaq_atomic_load_op": "This instruction loads 2^width^ bytes of memory from rs1 atomically and writes the result into rd."
  * "norm:ldaq_no_aq_reserved": "The versions without the aq bit set are RESERVED."
  * "norm:ldaq_rcsc_semantics": "The instruction always has an "acquire-RCsc" annotation, and if the bit rl is set the instruction ha..."
  * "norm:ldaq_rl_optional": "may have ordering annotation rl encoded in the instruction."
  * "norm:ldaq_rv64_only": "LD.{AQ, AQRL} is RV64-only."
  * "norm:ldaq_signext_rule": "If the size (2^width+3^) is less than XLEN, it is sign-extended to fill the destination register."
  * "norm:max_enc": "Encoding"
  * "norm:max_op": "Operation"
  * "norm:maxu_enc": "Encoding"
  * "norm:maxu_op": "Operation"
  * "norm:min_enc": "Encoding"
  * "norm:min_op": "Operation"
  * "norm:minu_enc": "Encoding"
  * "norm:minu_op": "Operation"
  * "norm:orc_b_enc": "Encoding"
  * "norm:orc_b_op": "Operation"
  * "norm:orn_enc": "Encoding"
  * "norm:orn_op": "Operation"
  * "norm:pack_enc": "Encoding"
  * "norm:pack_op": "Operation"
  * "norm:packh_enc": "Encoding"
  * "norm:packh_op": "Operation"
  * "norm:packw_enc": "Encoding"
  * "norm:packw_op": "Operation"
  * "norm:rev8_op": "Operation"
  * "norm:rev8_rv32_enc": "Encoding (RV32)"
  * "norm:rev8_rv64_enc": "Encoding (RV64)"
  * "norm:rol_enc": "Encoding"
  * "norm:rol_op": "Operation"
  * "norm:rolw_enc": "Encoding"
  * "norm:rolw_op": "Operation"
  * "norm:ror_enc": "Encoding"
  * "norm:ror_op": "Operation"
  * "norm:rori_op": "Operation"
  * "norm:rori_rv32_enc": "Encoding (RV32)"
  * "norm:rori_rv64_enc": "Encoding (RV64)"
  * "norm:roriw_enc": "Encoding"
  * "norm:roriw_op": "Operation"
  * "norm:rorw_enc": "Encoding"
  * "norm:rorw_op": "Operation"
  * "norm:rvwmo_aligned_amo_memop": "An aligned AMO gives rise to a single memory operation that
is both a load operation and a store ope..."
  * "norm:rvwmo_aligned_memop": "Each aligned memory instruction that accesses XLEN or
fewer bits gives rise to exactly one memory op..."
  * "norm:rvwmo_atomicity_axiom": "If r and w are paired load and store operations generated by aligned LR and SC instructions in a har..."
  * "norm:rvwmo_excludes_overlap_widths": "Memory consistency models supporting overlapping
memory accesses of different widths simultaneously ..."
  * "norm:rvwmo_fp_gt_xlen_memops": "A floating-point load or store of more than XLEN bits may
also be decomposed into a set of component..."
  * "norm:rvwmo_ld_val_axiom_lead-in": "Each byte of each load i returns the value written to that byte by the store that is the latest in g..."
  * "norm:rvwmo_ld_val_axiom_list": "Stores that write that byte and that precede i in the global memory order
Stores that write that byt..."
  * "norm:rvwmo_misaligned_in_atomic_pma": "if misaligned atomics are supported via the
misaligned atomicity granule PMA, then AMOs within an at..."
  * "norm:rvwmo_misaligned_ldst_memops": "A misaligned load or store instruction may be decomposed
into a set of component memory operations o..."
  * "norm:rvwmo_obeyed": "An execution of a RISC-V program obeys the RVWMO memory consistency model only if there exists a glo..."
  * "norm:rvwmo_only_mainmem": "This chapter defines the memory model for regular main memory
operations. The interaction of the mem..."
  * "norm:rvwmo_order_multi_memops": "The memory operations generated by such instructions
are not ordered with respect to each other in p..."
  * "norm:rvwmo_ppo_dep": "Syntactic Dependencies"
  * "norm:rvwmo_ppo_dep1": "b has a syntactic address dependency on a"
  * "norm:rvwmo_ppo_dep2": "b has a syntactic data dependency on a"
  * "norm:rvwmo_ppo_dep3": "b is a store, and b has a syntactic control dependency on a"
  * "norm:rvwmo_ppo_lead-in": "The complete definition of preserved program order is as follows (and note that AMOs are simultaneou..."
  * "norm:rvwmo_ppo_overlap": "Overlapping-Address Orderings"
  * "norm:rvwmo_ppo_overlap1": "b is a store, and a and b access overlapping memory addresses"
  * "norm:rvwmo_ppo_overlap2": "a and b are loads, x is a byte read by both a and
b, there is no store to x between a and b in progr..."
  * "norm:rvwmo_ppo_overlap3": "a is generated by an AMO or SC instruction, b is a load, and
b returns a value written by a"
  * "norm:rvwmo_ppo_pipe": "Pipeline Dependencies"
  * "norm:rvwmo_ppo_pipe1": "b is a load, and there exists some store m between a and b
in program order such that m has an addre..."
  * "norm:rvwmo_ppo_pipe2": "b is a store, and there exists some instruction m between a
and b in program order such that m has a..."
  * "norm:rvwmo_ppo_sync": "Explicit Synchronization"
  * "norm:rvwmo_ppo_sync1": "There is a FENCE instruction that orders a before b"
  * "norm:rvwmo_ppo_sync2": "a has an acquire annotation annotation"
  * "norm:rvwmo_ppo_sync3": "b has a release annotation"
  * "norm:rvwmo_ppo_sync4": "a and b both have RCsc annotations"
  * "norm:rvwmo_ppo_sync5": "a is paired with b"
  * "norm:rvwmo_progress_axiom": "No memory operation may be preceded in the global memory order by an infinite sequence of other memo..."
  * "norm:rvwmo_sc_fail_no_memop": "An unsuccessful SC instruction does not give rise to any memory operations."
  * "norm:rvwmo_single_copy_atomic": "All memory operations are single-copy atomic:
they can never be observed in a partially complete sta..."
  * "norm:rvwmo_single_hart_op": "Under RVWMO, code running on a single hart appears to execute in order
from the perspective of other..."
  * "norm:rvwmo_v_p_multi_memops": "ISA extensions such as V (Vector) and the upcoming P (SIMD)
may give rise to multiple memory operati..."
  * "norm:sdrl_aq_optional": "may have ordering annotation aq encoded in the instruction."
  * "norm:sdrl_atomic_store_enc": "Encoding"
  * "norm:sdrl_atomic_store_op": "This instruction stores 2^width^ bytes of memory from rs1 atomically."
  * "norm:sdrl_no_rl_reserved": "The versions without the rl bit set are RESERVED."
  * "norm:sdrl_rcsc_semantics": "The instruction always has an "release-RCsc" annotation, and if the bit aq is set the instruction ha..."
  * "norm:sdrl_rl_required": "This store must have ordering annotation rl"
  * "norm:sdrl_rv64_only": "SD.{RL, AQRL} is RV64-only."
  * "norm:seed_bist_latch": "Such a BIST alarm must be latched until polled at least once to enable
software to record its occurr..."
  * "norm:seed_csr_unpriv": "seed is an unprivileged CSR located at address 0x015."
  * "norm:seed_disable_if_weak": "If the security
level is under 256 bits, then the interface must not be available."
  * "norm:seed_entropy_unique": "Each returned seed[15:0] = entropy value represents unique randomness
when OPST=ES16 (seed[31:30] = ..."
  * "norm:seed_entropy_zero_non_es16": "When OPST is not ES16, entropy must be set to 0."
  * "norm:seed_exec_mode_control": "The seed CSR is also access controlled by execution mode, and attempted
read or write access will ra..."
  * "norm:seed_min_security_256": "Any implementation of the seed CSR that limits the security
strength shall not reduce it to less tha..."
  * "norm:seed_ro_illegal": "Attempts to access the seed CSR using a read-only CSR-access instruction
(CSRRS/CSRRC with rs1=x0 or..."
  * "norm:seed_wipe_on_read": "For security reasons, the interface guarantees that secret entropy
words are not made available mult..."
  * "norm:seed_write_ignore": "The write value (in rs1 or uimm) must be ignored by implementations."
  * "norm:sext_b_enc": "Encoding"
  * "norm:sext_b_op": "Operation"
  * "norm:sext_h_enc": "Encoding"
  * "norm:sext_h_op": "Operation"
  * "norm:sh1add_enc": "Encoding"
  * "norm:sh1add_op": "Operation"
  * "norm:sh1add_uw_enc": "Encoding"
  * "norm:sh1add_uw_op": "Operation"
  * "norm:sh2add_enc": "Encoding"
  * "norm:sh2add_op": "Operation"
  * "norm:sh2add_uw_enc": "Encoding"
  * "norm:sh2add_uw_op": "Operation"
  * "norm:sh3add_enc": "Encoding"
  * "norm:sh3add_op": "Operation"
  * "norm:sh3add_uw_enc": "Encoding"
  * "norm:sh3add_uw_op": "Operation"
  * "norm:sha256sig0_enc": "Encoding"
  * "norm:sha256sig0_op": "Operation"
  * "norm:sha256sig1_enc": "Encoding"
  * "norm:sha256sig1_op": "Operation"
  * "norm:sha256sum0_enc": "Encoding"
  * "norm:sha256sum0_op": "Operation"
  * "norm:sha256sum1_enc": "Encoding"
  * "norm:sha256sum1_op": "Operation"
  * "norm:sha512sig0_enc": "Encoding"
  * "norm:sha512sig0_op": "Operation"
  * "norm:sha512sig0h_enc": "Encoding"
  * "norm:sha512sig0h_op": "Operation"
  * "norm:sha512sig0l_enc": "Encoding"
  * "norm:sha512sig0l_op": "Operation"
  * "norm:sha512sig1_enc": "Encoding"
  * "norm:sha512sig1_op": "Operation"
  * "norm:sha512sig1h_enc": "Encoding"
  * "norm:sha512sig1h_op": "Operation"
  * "norm:sha512sig1l_enc": "Encoding"
  * "norm:sha512sig1l_op": "Operation"
  * "norm:sha512sum0_enc": "Encoding"
  * "norm:sha512sum0_op": "Operation"
  * "norm:sha512sum0r_enc": "Encoding"
  * "norm:sha512sum0r_op": "Operation"
  * "norm:sha512sum1_enc": "Encoding"
  * "norm:sha512sum1_op": "Operation"
  * "norm:sha512sum1r_enc": "Encoding"
  * "norm:sha512sum1r_op": "Operation"
  * "norm:slli_uw_enc": "Encoding"
  * "norm:slli_uw_op": "Operation"
  * "norm:sm3p0_enc": "Encoding"
  * "norm:sm3p0_op": "Operation"
  * "norm:sm3p1_enc": "Encoding"
  * "norm:sm3p1_op": "Operation"
  * "norm:sm4ed_enc": "Encoding"
  * "norm:sm4ed_op": "Operation"
  * "norm:sm4ks_enc": "Encoding"
  * "norm:sm4ks_op": "Operation"
  * "norm:twos_complement_signed_integers": "The base integer instruction sets use a two's-complement
representation for signed integer values."
  * "norm:unzip_enc": "Encoding"
  * "norm:unzip_op": "Operation"
  * "norm:vector_load_store_semantics": "Vector loads and stores move values between vector registers and
memory."
  * "norm:vector_masked_inactive_behavior": "Masked vector loads do not update inactive elements in the destination vector
register group, unless..."
  * "norm:vector_masked_memory_access": "Vector loads and stores can be masked, and they only access memory or raise
exceptions for active el..."
  * "norm:xlen_definition": "We use the term XLEN to refer to
the width of an integer register in bits (either 32 or 64)."
  * "norm:xnor_enc": "Encoding"
  * "norm:xnor_op": "Operation"
  * "norm:xperm4_enc": "Encoding"
  * "norm:xperm4_op": "Operation"
  * "norm:xperm8_enc": "Encoding"
  * "norm:xperm8_op": "Operation"
  * "norm:zalasr_atomic_ordered": "The Zalasr instructions are atomic loads and stores that support ordering annotations."
  * "norm:zalasr_builds_on_amo": "The Zalasr extension builds on the atomic support provided by the Zaamo (Atomic Memory Operations), ..."
  * "norm:zalasr_def": "The Zalasr (Load-Acquire and Store-Release) extension provides load-acquire and store-release instru..."
  * "norm:zalasr_ignore_rs2_upper": "ignore the upper bits of the value of rs2."
  * "norm:zalasr_misaligned_exception": "If the address is not naturally aligned, an address-misaligned exception or an access-fault exceptio..."
  * "norm:zalasr_misaligned_pma_relax": "The misaligned atomicity granule PMA, defined in Volume II of this manual, optionally relaxes this a..."
  * "norm:zalasr_misaligned_single_op": "If all accessed bytes lie within the same misaligned atomicity granule, the instruction will not rai..."
  * "norm:zalasr_natural_align": "The instructions in the Zalasr extension require that the address held in rs1 be naturally aligned t..."
  * "norm:zalasr_signext_rd": "The Zalasr instructions always sign-extend the value placed in rd"
  * "norm:zba_slli_uw_function": "While the shift and add instructions are limited to a maximum left shift of 3, the slli instruction ..."
  * "norm:zbb_orc_b_semantics": "orc.b sets the bits of each byte in the result rd to all zeros if no bit within the respective byte ..."
  * "norm:zbb_rotate_semantics": "where the shift-logical
instructions shift in zeros, the rotate instructions shift in the bits that ..."
  * "norm:zbb_sign_zero_extension_function": "These instructions perform the sign extension or zero extension of the least-significant 8 bits or 1..."
  * "norm:zbc_clmul_clmulh_results": "clmul produces the lower half of the carry-less product and clmulh produces the upper half of the 2{..."
  * "norm:zbc_clmulr_results": "clmulr produces bits 2{times}XLEN−2:XLEN-1 of the 2{times}XLEN carry-less product."
  * "norm:zbkx_indexing_behavior": "Elements in rs1 are replaced by the indexed element in rs2, or zero
if the index into rs2 is out of ..."
  * "norm:zbkx_lookup_table_model": "These instructions implement a "lookup table" for 4 and 8 bit elements
inside the general purpose re..."
  * "norm:zbs_single_bit_functionality": "The single-bit instructions provide a mechanism to set, clear, invert, or extract
a single bit in a ..."
  * "norm:zext_h_op": "Operation"
  * "norm:zext_h_rv32_enc": "Encoding (RV32)"
  * "norm:zext_h_rv64_enc": "Encoding (RV64)"
  * "norm:zicntr_rdcycleh_op": "RDCYCLEH is only present when XLEN=32 and reads bits 63-32
of the same cycle counter."
  * "norm:zicntr_rdinstreth_op": "RDINSTRETH is only
present when XLEN=32 and reads bits 63-32 of the same instruction
counter."
  * "norm:zicntr_rdtimeh_op": "RDTIMEH is only present when XLEN=32 and reads
bits 63-32 of the same real-time counter."
  * "norm:zicntr_time_hart_sync": "The real-time clocks of all harts must be synchronized to within one
tick of the real-time clock."
  * "norm:zihpm_op_sz_mode_acc_count": "RISC-V ISAs provide a set of up to thirty-two 64-bit performance
counters and timers"
  * "norm:zihpm_op_sz_mode_acc_partition": "These counters are
divided between the "Zicntr" and "Zihpm" extensions."
  * "norm:zihpm_op_sz_mode_acc_priv": "accessible via unprivileged XLEN-bit
read-only CSR registers 0xC00–0xC1F"
  * "norm:zihpm_op_sz_mode_acc_xlen32": "when XLEN=32, the upper 32 bits
are accessed via CSR registers 0xC80–0xC9F"
  * "norm:zip_enc": "Encoding"
  * "norm:zip_op": "Operation"
  * "norm:zk_impl_all": "A core which implements Zk must implement all of the above extensions."
  * "norm:zk_scalar_xreg_op": "All instructions described herein use the general-purpose X
registers, and obey the 2-read-1-write r..."
  * "norm:zkn_impl_all": "A core which implements Zkn must implement all of the above extensions."
  * "norm:zknd_shared_instr": "NOTE: The <<insns-aes64ks1i>> and <<insns-aes64ks2>> instructions are
presen..."
  * "norm:zkne_shared_instr": "NOTE: The
<<insns-aes64ks1i,aes64ks1i>>
and
<<insns-aes64ks2,aes64ks2>>
inst..."
  * "norm:zkr_seed_addr": "The entropy source extension defines the seed CSR at address 0x015. This CSR provides up to 16 physi..."
  * "norm:zks_impl_all": "A core which implements Zks must implement all of the above extensions."
  * "norm:zkt_impl_must_constant_latency": "if they claim to have Zkt and implement any of the listed instructions, it must have data-independen..."
  * "norm:zkt_optional_instr": "Vendors do not have to implement all of the list's instructions to be Zkt
compliant;"

Deleted 3 tags:
  * "norm:jvt_en": "If the Smstateen extension is implemented, then bit 2 in mstateen0, sstateen0, and hstateen0 is impl..."
  * "norm:test_ci_workflow_rule": "This is a test normative rule to verify the CI workflow creates issues for new additions."
  * "norm:zihpm_op_sz_mode_acc": "RISC-V ISAs provide a set of up to thirty-two 64-bit performance counters and timers that are access..."

Modified 8 tags:
  * "norm:csr_rs1_uimm_side_effect":
      Reference: "The CSRRS[I] an CSRRC[I] instructions
only action side effects for fields for which the rs1 or uimm ..."
      Current:   "The CSRRS[I] and CSRRC[I] instructions
only action side effects for fields for which the rs1 or uimm..."
  * "norm:hpmcounter_op_sz_mode":
      Reference: "The Zihpm extension comprises up to 29 additional unprivileged 64-bit
hardware performance counters,..."
      Current:   "The Zihpm extension comprises up to 29 additional unprivileged 64-bit
hardware performance counters,..."
  * "norm:vsha2chl-vv_op_sew64":
      Reference: "SEW=64: 2 rounds of SHA-512 compression are performed (zvkhnb)"
      Current:   "SEW=64: 2 rounds of SHA-512 compression are performed (zvknhb)"
  * "norm:vsha2ms-vv_op_sew64":
      Reference: "SEW=64: Four rounds of SHA-512 message schedule expansion are performed (zvkhnb)"
      Current:   "SEW=64: Four rounds of SHA-512 message schedule expansion are performed (zvknhb)"
  * "norm:vsm4r_op_sm4encdec":
      Reference: "The four words of current state are read as a 4-element group from 'vd'
and the round keys are read ..."
      Current:   "The four words of current state are read as a 4-element group from vd
and the round keys are read fr..."
  * "norm:zicntr_rdcycle_op":
      Reference: "The RDCYCLE pseudoinstruction reads the low XLEN bits of the cycle
CSR which holds a count of the nu..."
      Current:   "The RDCYCLE pseudoinstruction reads the low XLEN bits of the cycle
CSR which holds a count of the nu..."
  * "norm:zicntr_rdinstret_op":
      Reference: "The RDINSTRET pseudoinstruction reads the low XLEN bits of the
instret CSR, which counts the number ..."
      Current:   "The RDINSTRET pseudoinstruction reads the low XLEN bits of the
instret CSR, which counts the number ..."
  * "norm:zicntr_rdtime_op":
      Reference: "The RDTIME pseudoinstruction reads the low XLEN bits of the "time" CSR,
which counts wall-clock real..."
      Current:   "The RDTIME pseudoinstruction reads the low XLEN bits of the "time" CSR,
which counts wall-clock real..."

================================================================================
Summary: 320 total changes
  Added:    309
  Deleted:  3
  Modified: 8
================================================================================

Privileged Specification

================================================================================
Tag Changes Report
================================================================================

Reference file: ref/riscv-privileged-norm-tags.json
Current file: build/riscv-privileged-norm-tags.json
Added 322 tags:
  * "norm:LCOFIP_op": "When an OF bit is set, it eventually, but not necessarily immediately, sets
the LCOFIP bit in the mi..."
  * "norm:Smrnmi_csrs": "The extension adds four new CSRs (mnepc, mncause,
mnstatus, and mnscratch) to hold the interrupted s..."
  * "norm:Ssqosid_cbqri_spec": "These identifiers are crucial for the RISC-V Capacity and Bandwidth Controller
QoS Register Interfac..."
  * "norm:Ssqosid_hw_monitoring_required": "To manage performance variability, system software needs resource allocation and
monitoring capabili..."
  * "norm:Ssqosid_metadata_used_by_controllers": "Additional metadata, like the nature of the memory access and the ID of the
originating supervisor d..."
  * "norm:Ssqosid_rcid_mcid_accompany_requests": "The RCID and MCID accompany each request made by the hart to shared resource
controllers. The RCID i..."
  * "norm:Ssqosid_shared_resource_need_management": "When multiple workloads execute concurrently on modern processors—equipped with
large core counts, m..."
  * "norm:Ssqosid_smstateen_srmcfg_requires_mstateen0": "If extension Smstateen is implemented together with Ssqosid, then Ssqosid also
requires the SRMCFG b..."
  * "norm:Ssqosid_srmcfg_access_illegal_instruction": "If mstateen0.SRMCFG is 0, attempts to access srmcfg in privilege modes
less privileged than M-mode r..."
  * "norm:Ssqosid_srmcfg_access_virtual_instruction": "If mstateen0.SRMCFG is 1 or if extension Smstateen is not implemented,
attempts to access srmcfg whe..."
  * "norm:Ssqosid_srmcfg_csr_applies_to_all_modes": "The RCID and MCID configured in the srmcfg CSR apply to all privilege
modes of software execution on..."
  * "norm:Ssqosid_srmcfg_introduced": "To facilitate this, the QoS Identifiers extension (Ssqosid) introduces the
srmcfg register, which co..."
  * "norm:Ssqosid_srmcfg_register_size": "The srmcfg register is an SXLEN-bit read/write register used to configure a
Resource Control ID (RCI..."
  * "norm:Sv39_LEVELS": "LEVELS equals 3"
  * "norm:Sv39_PTESIZE": "PTESIZE equals 8"
  * "norm:Sv39_leaf_any_level": "Any level of PTE may be a leaf PTE"
  * "norm:Sv39_levels": "three-level page table"
  * "norm:Sv39_page_offset_sz": "12-bit page offset is untranslated"
  * "norm:Sv39_page_sizes": "2 MiB megapages and 1 GiB gigapages"
  * "norm:Sv39_pt_align": "must always be aligned to a page boundary"
  * "norm:Sv39_pt_sz": "exactly the size of a page"
  * "norm:Sv39_pte_count": "2^9^ page table entries
(PTEs)"
  * "norm:Sv39_pte_future_rsv": "must be zeroed by software for forward
compatibility. If any of these bits are set, a page-fault exc..."
  * "norm:Sv39_pte_svnapot_rsv": "If Svnapot is not implemented, bit 63 remains
reserved and must be zeroed by software for forward co..."
  * "norm:Sv39_pte_svpbmt_rsv": "If Svpbmt is not implemented, bits 62-61 remain
reserved and must be zeroed by software for forward ..."
  * "norm:Sv39_pte_sz": "eight bytes each"
  * "norm:Sv39_superpage_align": "must be virtually and physically
aligned to a boundary equal to its size"
  * "norm:Sv39_superpage_align_fault": "A page-fault exception is raised if
the physical address is insufficiently aligned"
  * "norm:Sv39_sxlen": "simple paged virtual-memory system for
SXLEN=64"
  * "norm:Sv39_va_signext": "must have bits 63–39 all equal to bit 38, or else
a page-fault exception will occur"
  * "norm:Sv39_va_sz": "supports 39-bit virtual address spaces"
  * "norm:Sv39_vpn_sz": "27-bit VPN"
  * "norm:Sv48_LEVELS": "LEVELS equals 4"
  * "norm:Sv48_PTESIZE": "PTESIZE equals 8"
  * "norm:Sv48_leaf_any_level": "Any level of PTE may be a leaf PTE"
  * "norm:Sv48_levels": "four-level page table"
  * "norm:Sv48_page_offset_sz": "12-bit page offset is untranslated"
  * "norm:Sv48_page_sizes": "2 MiB megapages, 1 GiB gigapages, and
512 GiB terapages"
  * "norm:Sv48_requires_Sv39": "Implementations that support Sv48 must also
support Sv39"
  * "norm:Sv48_superpage_align": "must be virtually and physically aligned to
a boundary equal to its size"
  * "norm:Sv48_superpage_align_fault": "A page-fault exception is raised if
the physical address is insufficiently aligned"
  * "norm:Sv48_sxlen": "SXLEN=64"
  * "norm:Sv48_va_signext": "must have bits 63–48 all equal to bit 47, or else
a page-fault exception will occur"
  * "norm:Sv48_va_sz": "48-bit virtual address spaces"
  * "norm:Sv48_vpn_sz": "36-bit VPN"
  * "norm:Sv57_LEVELS": "LEVELS equals 5"
  * "norm:Sv57_PTESIZE": "PTESIZE equals 8"
  * "norm:Sv57_leaf_any_level": "Any level of PTE may be a leaf PTE"
  * "norm:Sv57_levels": "five-level page table"
  * "norm:Sv57_page_offset_sz": "12-bit page offset is untranslated"
  * "norm:Sv57_page_sizes": "2 MiB megapages, 1 GiB gigapages, 512 GiB
terapages, and 256 TiB petapages"
  * "norm:Sv57_requires_Sv48": "Implementations that support Sv57 must also
support Sv48"
  * "norm:Sv57_superpage_align": "must be virtually and physically aligned to
a boundary equal to its size"
  * "norm:Sv57_superpage_align_fault": "A page-fault exception is raised if
the physical address is insufficiently aligned"
  * "norm:Sv57_sxlen": "RV64 systems"
  * "norm:Sv57_va_signext": "must have bits 63–57 all equal to bit 56, or else
a page-fault exception will occur"
  * "norm:Sv57_va_sz": "57-bit virtual address spaces"
  * "norm:Sv57_vpn_sz": "45-bit VPN"
  * "norm:Svadu_disabled_hw_update_falls_back_to_svade": "When hardware updating of A/D bits is disabled, the Svade extension,
which mandates exceptions when ..."
  * "norm:Svadu_hw_update_a_d_bits": "If the Svadu extension is implemented, the menvcfg.ADUE field is writable."
  * "norm:Svadu_hypervisor_adue_writable": "If the hypervisor extension is additionally implemented, the henvcfg.ADUE
field is also writable."
  * "norm:Svinval_hinval_gvma_uses_vmid": "HINVAL.GVMA uses VMIDs instead of ASIDs."
  * "norm:Svinval_hinval_vvma_gvma": "These have the same semantics as SINVAL.VMA, except that they combine with
SFENCE.W.INVAL and SFENCE..."
  * "norm:Svinval_illegal_instruction_tvm": "An attempt to execute SINVAL.VMA or HINVAL.GVMA in S-mode or HS-mode when
mstatus.TVM=1 also raises ..."
  * "norm:Svinval_illegal_instruction_u_mode": "In particular, an attempt to execute any of
these instructions in U-mode always raises an illegal-in..."
  * "norm:Svinval_sequence_reads_writes_after": "reads and writes following the SFENCE.INVAL.IR are considered to be
those subsequent to the SFENCE.V..."
  * "norm:Svinval_sequence_reads_writes_before": "reads and writes prior to the SFENCE.W.INVAL are considered to be
those prior to the SFENCE.VMA,"
  * "norm:Svinval_sequence_rs1_rs2": "the values of rs1 and rs2 for the SFENCE.VMA are the same as those
used in the SINVAL.VMA,"
  * "norm:Svinval_sfence_w_inval_inval_s_vs_mode": "SFENCE.W.INVAL and SFENCE.INVAL.IR are unaffected by the mstatus.TVM and
hstatus.VTVM fields and hen..."
  * "norm:Svinval_sfence_w_inval_inval_u_mode": "raises an illegal-instruction exception."
  * "norm:Svinval_sfence_w_inval_inval_vu_mode": "Doing so in VU-mode raises a virtual-instruction exception."
  * "norm:Svinval_sfence_w_inval_orders_before_sinval_vma": "The SFENCE.INVAL.IR
instruction guarantees that any previous SINVAL.VMA instructions executed
by the..."
  * "norm:Svinval_sinval_vma_invalidates_same_as_sfence_vma": "However, unlike SFENCE.VMA, SINVAL.VMA
instructions are only ordered with respect to SFENCE.VMA,
SFE..."
  * "norm:Svinval_split_fine_grained": "that can be more efficiently batched or pipelined on certain classes of
high-performance implementat..."
  * "norm:Svinval_virtual_instruction_vtvms": "When hstatus.VTVM=1, an attempt to execute SINVAL.VMA in VS-mode also raises
a virtual-instruction e..."
  * "norm:Svinval_virtual_instruction_vu_vs": "An attempt to execute HINVAL.VVMA or HINVAL.GVMA in VS-mode or VU-mode, or to
execute SINVAL.VMA in ..."
  * "norm:Svnapot_cache_entries": "Implicit reads of NAPOT page table entries
may create address-translation cache entries mapping
a + ..."
  * "norm:Svnapot_depends_Sv39": "The Svnapot extension depends on the Sv39
extension"
  * "norm:Svnapot_hyp_gstage": "Svnapot is also supported in G-stage
translation"
  * "norm:Svnapot_implicit_read_ppn_subst": "implicit reads of a NAPOT PTE
return a copy of pte in which pte.ppn[i][pte.napot_bits-1:0]
is replac..."
  * "norm:Svnapot_pte_N": "N=1"
  * "norm:Svnapot_range_napot": "Such ranges must be of a naturally aligned
power-of-2 (NAPOT) granularity larger than the base page ..."
  * "norm:Svnapot_reserved_encoding_fault": "reserved according to
<<ptenapot>>, then a page-fault exception must be raised"
  * "norm:Svnapot_valid_encoding": "valid according to <<ptenapot>>"
  * "norm:Svpbmt_aliasing_attribute": "When Svpbmt is used with non-zero PBMT encodings, it is possible for
multiple virtual aliases of the..."
  * "norm:Svpbmt_cacheable_aliasing_fence_flush_fence_required": "prevents both loss of coherence and loss of memory ordering:"
  * "norm:Svpbmt_cacheable_aliasing_may_cause_coherence_loss": "may
cause loss of coherence."
  * "norm:Svpbmt_depends_Sv39": "The Svpbmt extension depends on the Sv39 extension"
  * "norm:Svpbmt_hgatp_stage_override_rule": "if hgatp.MODE is not equal to zero, non-zero G-stage PTE PBMT bits
override the attributes in the PM..."
  * "norm:Svpbmt_impl_may_override_pmas": "Implementations may override additional PMAs not explicitly listed in
<<pbmt>>."
  * "norm:Svpbmt_io_pma_nc_pbmt_obey_rvwmo": "If the underlying physical memory attribute for a page is I/O, and the
page has PBMT=NC, then
access..."
  * "norm:Svpbmt_io_pma_nc_pbmt_treated_as_io_and_memory": "accesses to such pages are considered to be both I/O and main memory
accesses for the purposes of FE..."
  * "norm:Svpbmt_leaf_pte_pbmt_reserved_3_fault": "Until this value is defined by a standard extension, using
this reserved value in a leaf PTE raises ..."
  * "norm:Svpbmt_memory_pma_io_pbmt_strong_io_ordering": "accesses to that page obey strong channel
0 I/O ordering rules."
  * "norm:Svpbmt_memory_pma_io_pbmt_treated_as_io_and_memory": "accesses to
such pages are considered to be both I/O and main memory accesses for
the purposes of FE..."
  * "norm:Svpbmt_noncacheable_aliasing_fence_prevents_ordering_loss": "fence iorw, iorw instruction
between such accesses suffices to prevent loss of memory ordering."
  * "norm:Svpbmt_noncacheable_aliasing_may_weaken_ordering": "might result in weaker memory ordering than the stricter attribute
ordinarily guarantees."
  * "norm:Svpbmt_noncacheable_aliasing_no_coherence_loss": "Accessing the same location using different attributes that are both
non-cacheable (e.g., NC and IO)..."
  * "norm:Svpbmt_nonleaf_pte_pbmt_must_be_zero": "Until their use is defined by a standard extension, they must be cleared
by software for forward com..."
  * "norm:Svpbmt_obeys_mem_ordering": "memory accesses to such pages obey the memory ordering rules of the
final effective attribute,"
  * "norm:Svpbmt_vsatp_stage_override_rule": "if vsatp.MODE is not equal to zero, non-zero VS-stage PTE PBMT
bits override the intermediate attrib..."
  * "norm:Svrsw60t59b_depends_on_sv39": "The Svrsw60t59b extension depends on Sv39."
  * "norm:Svrsw60t59b_h_g_stage_reserved_bits": "If the Hypervisor (H) extension is also implemented, then bits 60-59 of the
G-stage PTEs are reserve..."
  * "norm:Svrsw60t59b_reserved_bits_60_59": "If the Svrsw60t59b extension is implemented, then bits 60-59 of the page table
entries (PTEs) are re..."
  * "norm:Svvptc_explicit_stores_update_valid_bit": "When the Svvptc extension is implemented, explicit stores by a hart that update
the Valid bit of lea..."
  * "norm:Zicfilp_exception_priority": "The software-check exception caused by Zicfilp has higher priority than an illegal-instruction excep..."
  * "norm:Zicfilp_forward_trap_async_exception": "Synchronous exceptions with priority higher than that of a software-check
exception with xtval set t..."
  * "norm:Zicfilp_forward_trap_async_interrupt": "Asynchronous interrupts."
  * "norm:Zicfilp_forward_traps": "A trap may need to be delivered to the same or to a higher privilege mode upon
completion of JALR/C...."
  * "norm:Zicfilp_pelp_debug_mode": "Upon entry into Debug Mode, the pelp bit in dcsr is updated with the ELP at the privilege level the ..."
  * "norm:Zicfilp_pelp_trap": "When a trap is taken into privilege mode x, the xPELP is set to ELP and ELP is set to NO_LP_EXPECTED..."
  * "norm:Zicfilp_pelp_trap_return": "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively.  When e..."
  * "norm:all_xinh_zero": "When all xINH bits are zero, event counting is enabled in all modes."
  * "norm:bootrom_discovery": "It is expected that BootROM will set mseccfg.MMWP and/or mseccfg.MML during early boot, before jumpi..."
  * "norm:count_overflow_interrupt": "If an hpmcounter overflows while the associated OF bit is zero, then a "count overflow interrupt req..."
  * "norm:count_overflow_trigger": "Count overflow never results from writes to the mhpmcountern or mhpmeventn registers, only from hard..."
  * "norm:counter_inhibited_behavior": "The fundamental behavior of cycle and instret is modified in that counting does not occur while exec..."
  * "norm:csr_access": "A CSR
accessible via one method may or may not be accessible via the other
method."
  * "norm:csr_supervisor_access": "The content of these registers may be accessible from Supervisor level if the Smcdeleg/Ssccfg extens..."
  * "norm:csrs_alias": "Machine-level and
Supervisor-level CSRs with the same select value may be defined by an
extension as..."
  * "norm:cycle_counting": "The cycle counter will simply count CPU cycles while the CPU is in a non-inhibited privilege mode."
  * "norm:hpmcounter_overflow": "Since hpmcounter values are unsigned values,
overflow is defined as unsigned overflow of the impleme..."
  * "norm:hstateen-bit-63_op": "Likewise, bit 63 of each hstateen
correspondingly controls access to the matching sstateen CSR."
  * "norm:hstateen-bit-63_writable": "Bit 63 of each hstateen CSR is always writable (not
read-only)."
  * "norm:hstateen0-SE0_op": "The SE0 bit in hstateen0 controls access to the
sstateen0 CSR."
  * "norm:hstateen0-aia_op": "The AIA bit in hstateen0 controls access to all state introduced by the
Ssaia extension and not cont..."
  * "norm:hstateen0-context_op": "The CONTEXT bit in
hstateen0 controls access to the scontext CSR provided by the Sdtrig
extension."
  * "norm:hstateen0-csrind_op": "The CSRIND bit in hstateen0 controls access to the siselect and the
sireg*, (really vsiselect and vs..."
  * "norm:hstateen0-envcfg_op": "The ENVCFG bit in hstateen0 controls access to the
senvcfg CSRs."
  * "norm:hstateen0-imsic_op": "The IMSIC bit in
hstateen0 controls access to the guest IMSIC state, including CSRs stopei
(really v..."
  * "norm:hstateen_encoding": "With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen CSRs, exce..."
  * "norm:hstateen_ro1_bits": "A bit in an hstateen CSR cannot be read-only one
unless the same bit is read-only one in the matchin..."
  * "norm:hstateen_sstateen_zero_initialization": "If machine-level software changes these values, it is responsible for
initializing the corresponding..."
  * "norm:hypervisor_impl_csrs_access_control": "If the hypervisor extension is implemented, the same bit is defined also in hypervisor CSR hstateen0..."
  * "norm:instret_exception": "The former are not considered to retire, and hence do not increment instret."
  * "norm:instret_non_inhibited": "instructions that retire in a non-inhibited mode increment instret, and instructions that retire in ..."
  * "norm:instret_xret": "The latter do retire, and should increment instret only if the originating privilege mode is not inh..."
  * "norm:m_mode_perf_monitoring": "M-mode includes a basic hardware performance-monitoring facility."
  * "norm:mcyclecfg_op": "configure privilege mode filtering for the cycle and instret counters, respectively."
  * "norm:mcyclecfg_sz": "mcyclecfg and minstretcfg are 64-bit registers"
  * "norm:mhpmevent-INH_op": "Each of the five xINH bits, when set, inhibit counting of events while in privilege mode x. All-zero..."
  * "norm:mhpmevent-OF_bit_Set": "Generation of a count-overflow-interrupt request by an hpmcounter sets the
associated OF bit."
  * "norm:mhpmevent-OF_op": "The OF bit is set when the corresponding hpmcounter overflows, and remains set
until written by soft..."
  * "norm:miph_csr_number": "The mireg* CSR numbers are not consecutive because miph is CSR number 0x354."
  * "norm:mireg_access_behaviour": "Ordinarily, each `mireg`i will access register state, access read-only 0 state, or raise an illegal-..."
  * "norm:mireg_access_on_legal_miselect": "Attempts to access mireg* while miselect holds a number in an allocated and implemented range result..."
  * "norm:miselect-msb_op": "Values of miselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for cust..."
  * "norm:miselect_WARL": "miselect is a WARL
register."
  * "norm:miselect_min_sz": "The miselect register implements at least enough bits to support all
implemented miselect values (co..."
  * "norm:miselect_op": "The value of miselect determines which
register is accessed upon read or write of each of the machin..."
  * "norm:miselect_value_range": "miselect value ranges are allocated to dependent
extensions, which specify the register state access..."
  * "norm:mml_truth_table": "The physical memory protection rules when mseccfg.MML is set to 1 are summarized in the truth table ..."
  * "norm:mncause_doubletrap": "If the reason is an exception within M-mode that results in a double trap as
specified in the Smdblt..."
  * "norm:mncause_interrupt": "If the reason is an interrupt, bit MXLEN-1 is set to 1,"
  * "norm:mncause_interrupt_code": "the RNMI
cause is encoded in the least-significant bits."
  * "norm:mncause_interrupt_zero": "If the reason is an interrupt and RNMI causes are not supported, bit MXLEN-1 is
set to 1, and zero i..."
  * "norm:mncause_op": "The mncause CSR holds the reason for the RNMI."
  * "norm:mnepc_acc": "read-write register"
  * "norm:mnepc_bit0": "The low bit of mnepc (mnepc[0]) is always zero."
  * "norm:mnepc_bit1_writable": "Though masked, mnepc[1]
remains writable when IALIGN=32."
  * "norm:mnepc_ialign32": "On implementations
that support only IALIGN=32, the two low bits (mnepc[1:0]) are always
zero."
  * "norm:mnepc_ialign_mask": "If an implementation allows IALIGN to be either 16 or 32 (by changing
CSR misa, for example), then, ..."
  * "norm:mnepc_invalid_convert": "Prior to writing mnepc, implementations may convert an
invalid address into some other invalid addre..."
  * "norm:mnepc_op": "RNMI trap handler holds the PC of the instruction that took the
interrupt."
  * "norm:mnepc_sz": "The mnepc CSR is an MXLEN-bit"
  * "norm:mnepc_warl": "mnepc is a WARL register that must be able to hold all valid virtual
addresses."
  * "norm:mnret_exist": "one new
instruction, MNRET, to resume from the RNMI handler."
  * "norm:mnret_mode": "MNRET is an M-mode-only instruction"
  * "norm:mnret_mprv": "If MNRET changes the privilege mode to a mode less privileged than M, it also sets mstatus.MPRV to 0..."
  * "norm:mnret_restore": "This instruction also
sets mnstatus.NMIE."
  * "norm:mnret_zicfilp": "If the Zicfilp extension is implemented, then if the new privileged mode
is y, MNRET sets ELP to the..."
  * "norm:mnscratch_acc": "read-write register"
  * "norm:mnscratch_op": "enables
the RNMI trap handler to save and restore the context that was
interrupted."
  * "norm:mnscratch_sz": "The mnscratch CSR holds an MXLEN-bit"
  * "norm:mnstatus_mnpelp_op": "If the Zicfilp extension is implemented, mnstatus also holds the MNPELP
field, which on entry to the..."
  * "norm:mnstatus_mnpelp_update": "When an RNMI trap is taken, MNPELP is set to ELP and ELP is set to 0."
  * "norm:mnstatus_mnpp_op": "The mnstatus CSR holds a two-bit field, MNPP, which on entry to the
RNMI trap handler holds the priv..."
  * "norm:mnstatus_mnpv_op": "It also holds a one-bit
field, MNPV, which on entry to the RNMI trap handler holds the virtualizatio..."
  * "norm:mnstatus_mprv_clear": "When NMIE=0, the hart behaves as though mstatus.MPRV were clear,
regardless of the current setting o..."
  * "norm:mnstatus_nmie_disable": "When NMIE=0, all interrupts are disabled."
  * "norm:mnstatus_nmie_enable": "When NMIE=1, non-maskable interrupts
are enabled."
  * "norm:mnstatus_nmie_reset": "Upon reset, NMIE contains the value 0."
  * "norm:mnstatus_nmie_set_clear": "Software can set NMIE to 1, but attempts to clear NMIE have no effect."
  * "norm:mnstatus_reserved": "The other bits in mnstatus are reserved; software should write zeros
and hardware implementations sh..."
  * "norm:mnstatus_wfi": "For the purposes of the WFI instruction, NMIE is a global interrupt
enable, meaning that the setting..."
  * "norm:mseccfg_fields_exist": "this
extension introduces the RLB, MMWP, and MML fields in the mseccfg CSR
and their associated rule..."
  * "norm:mseccfg_locking": "Since all fields defined in mseccfg as part of this extension are locked when set (MMWP/MML) or lock..."
  * "norm:mstateen-bit-63_op": "For each mstateen CSR, bit 63 is defined to control access to the
matching sstateen and hstateen CSR..."
  * "norm:mstateen-bit-63_roz": "Bit 63 of each mstateen CSR may be read-only zero only if the hypervisor
extension is not implemente..."
  * "norm:mstateen0-aia_op": "The AIA bit in mstateen0 controls access to all state introduced by the
Ssaia extension and not cont..."
  * "norm:mstateen0-context_op": "The CONTEXT bit in mstateen0 controls access to the scontext and
hcontext CSRs provided by the Sdtri..."
  * "norm:mstateen0-csrind_op": "The CSRIND bit in mstateen0 controls access to the siselect, sireg*,
vsiselect, and the vsireg* CSRs..."
  * "norm:mstateen0-envcfg_op": "The ENVCFG bit in mstateen0 controls access to the henvcfg, henvcfgh,
and the senvcfg CSRs."
  * "norm:mstateen0-imsic_op": "The IMSIC bit in mstateen0 controls access to the IMSIC state, including
CSRs stopei and vstopei, pr..."
  * "norm:mstateen0-p1p13_op": "The P1P13 bit in mstateen0 controls access to the hedelegh introduced by Privileged Specification Ve..."
  * "norm:mstateen0-se0_op": "The SE0 bit in mstateen0 controls access to the hstateen0, hstateen0h,
and the sstateen0 CSRs."
  * "norm:mstateen0-srmcfg_op": "The SRMCFG bit in mstateen0 controls access to the srmcfg CSR introduced by the Ssqosid  extension."
  * "norm:mstateen_bit_allocation": "The intention is to allocate bits
for this purpose starting at the most-significant end, bit 63, thr..."
  * "norm:mstateen_bit_encroachment": "If the rate that bits are
being allocated from the least-significant end for sstateen CSRs is
suffic..."
  * "norm:mstateen_zero_initialization": "On reset, all writable mstateen bits are initialized by the hardware to zeros."
  * "norm:pm_all_priv_modes": "Such tools can be applied in all privilege modes (U, S, and M)."
  * "norm:pm_apply_explicit": "When pointer masking is enabled, the ignore transformation will be applied to every explicit memory ..."
  * "norm:pm_auto_apply_active_mode": "Different privilege modes may have different pointer masking settings active simultaneously and the ..."
  * "norm:pm_config_next_higher": "A privilege mode's pointer masking setting is configured by bits in configuration registers of the n..."
  * "norm:pm_cpu_only": "Pointer masking only applies to accesses generated by instructions on the CPU (including CPU extensi..."
  * "norm:pm_csr_hw_apply": "pointer masking, when applicable, is applied for hardware writes to a CSR (e.g., when the hardware w..."
  * "norm:pm_debug_trigger": "Pointer masking is also applied, when applicable, to the memory access address when matching address..."
  * "norm:pm_deterministic_effect": "Pointer masking with the same value of PMLEN always has the same effect for the same type of address..."
  * "norm:pm_family_extensions": "Pointer masking refers to a number of separate extensions, all of which are privileged."
  * "norm:pm_ignore_pa": "When applied to a physical address, including guest-physical addresses (i.e., all cases except when ..."
  * "norm:pm_ignore_upper_bits": "RISC-V Pointer Masking (PM) is a feature that, when enabled, causes the CPU to ignore the upper bits..."
  * "norm:pm_ignore_va": "The ignore transformation differs depending on whether it applies to a virtual or physical address. ..."
  * "norm:pm_misaligned_equivalence": "Misaligned accesses are supported, subject to the same limitations as in the absence of pointer mask..."
  * "norm:pm_mode_only_dependency": "the pointer masking setting that is applied only depends on the active privilege mode, not on the ad..."
  * "norm:pm_mprv_spvp": "MPRV and SPVP affect pointer masking as well, causing the pointer masking settings of the effective ..."
  * "norm:pm_mxr_exception": "When MXR is in effect at the effective privilege mode where explicit memory access is performed, poi..."
  * "norm:pm_no_csr_sw": "No pointer masking operations are applied when software reads/writes to CSRs, including those meant ..."
  * "norm:pm_no_trap_vector_mask": "on trap delivery (e.g., due to an exception or interrupt), pointer masking will not be applied to th..."
  * "norm:pm_not_apply_implicit": "The transformation does not apply to implicit accesses such as page-table walks or instruction fetch..."
  * "norm:pm_per_mode_control": "Pointer masking is controlled separately for different privilege modes."
  * "norm:pm_rv32_illegal": "In RV32, trying to enable pointer masking will result in an illegal WARL write and not update the po..."
  * "norm:pm_rv64_only": "Pointer masking only applies to RV64."
  * "norm:pm_tag_check_impl": "The tag checks themselves can be implemented in software or hardware."
  * "norm:pm_uxl_clear": "Setting UXL/SXL/MXL to 1 will clear the corresponding pointer masking configuration bits."
  * "norm:pm_warl_unaffected": "The implemented WARL width of CSRs is unaffected by pointer masking"
  * "norm:pmlen_future_reserved": "A setting has been reserved to potentially support other values of PMLEN in future standards."
  * "norm:pmlen_illegal_warl": "Trying to enable pointer masking in an unsupported scenario represents an illegal write to the corre..."
  * "norm:pmlen_mode_depend": "the supported values of PMLEN may depend on the effective privilege mode. The current standard only ..."
  * "norm:pmlen_supported_values": "The current standard only supports PMLEN=XLEN-48 (i.e., PMLEN=16 in RV64) and PMLEN=XLEN-57 (i.e., P..."
  * "norm:rnmi_enter_mmode": "The hart then enters machine-mode and jumps to the RNMI trap handler
address."
  * "norm:rnmi_entry": "When an RNMI interrupt is detected, the interrupted PC is written to the
mnepc CSR,"
  * "norm:rnmi_entry_cause": "the type of RNMI to the mncause CSR,"
  * "norm:rnmi_entry_nmie_clear": "The
mnstatus.NMIE bit is cleared, masking all interrupts."
  * "norm:rnmi_entry_priv": "the privilege
mode of the interrupted context to the mnstatus CSR."
  * "norm:rnmi_exc_trap_addr": "RNMI also has an associated exception trap handler address, which is
implementation defined."
  * "norm:rnmi_exception_nmie0": "If the hart encounters an exception while executing in M-mode with the mnstatus.NMIE bit clear, the ..."
  * "norm:rnmi_not_disabled": "cannot be disabled by software. Specifically, they are not disabled
by clearing the mstatus.MIE regi..."
  * "norm:rnmi_priority": "These interrupts
have higher priority than any other interrupt or exception on the hart"
  * "norm:rnmi_resume": "The RNMI handler can resume original execution using the new MNRET
instruction, which restores the P..."
  * "norm:rnmi_trap_addr": "The RNMI interrupt trap handler address is implementation-defined."
  * "norm:rv32_high_access": "For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstret..."
  * "norm:satp-ppn_sv39_sz": "44-bit PPN"
  * "norm:satp-ppn_sv48_sz": "44-bit PPN"
  * "norm:satp-ppn_sv57_sz": "44-bit PPN"
  * "norm:scountovf_mmode_read_access": "In M-mode, scountovf bit X is always readable."
  * "norm:scountovf_op": "This extension adds the scountovf CSR, a 32-bit read-only register that contains shadow copies of th..."
  * "norm:scountovf_smode_read_access": "In S/HS-mode, scountovf bit X is readable when mcounteren bit
X is set, and otherwise reads as zero."
  * "norm:scountovf_smode_read_access_control": "Read access to bit X is subject to the same mcounteren (or mcounteren and
hcounteren) CSRs that medi..."
  * "norm:scountovf_vsmode_read_access": "Similarly, in VS mode, scountovf bit
X is readable when mcounteren bit X and hcounteren bit X are bo..."
  * "norm:select_value_separate_address_space": "Select values are a separate address space from CSR numbers, and
from tselect values in the Sdtrig e..."
  * "norm:select_value_unrelated": "If a CSR is both directly
and indirectly accessible, the CSR's select value is unrelated to its
CSR ..."
  * "norm:sireg_access_behaviour": "Ordinarily, each `sireg`i will access register state, access read-only 0 state, or, unless executing..."
  * "norm:sireg_access_on_illegal_siselect": "The behavior upon accessing sireg* from M-mode or S-mode, while siselect holds a value that is not i..."
  * "norm:sireg_access_on_legal_siselect": "Otherwise, attempts to access sireg* from M-mode or S-mode while siselect holds a number in a standa..."
  * "norm:siselect-msb_op": "Values of siselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for cust..."
  * "norm:siselect_min_range": "The siselect register will support the value range 0..0xFFF at a
minimum."
  * "norm:smcdeleg_cde_en": "When the Smcdeleg/Ssccfg extensions are enabled (menvcfg.CDE=1), it further allows M-mode to delegat..."
  * "norm:smcdeleg_ssccfg_tandem": "For a RISC-V hardware platform, Smcdeleg and Ssccfg must always be implemented in tandem."
  * "norm:smepmp_attack_surface": "Without being able to protect less-privileged modes from Machine mode, it is not possible to prevent..."
  * "norm:smepmp_machine_unlimited": "So for any physical memory region which is not protected with a Locked rule, Machine mode has unlimi..."
  * "norm:smepmp_no_mml_behavior": "It is only possible to have a locked rule that will be enforced on all modes, or a rule that will be..."
  * "norm:smepmp_no_mml_limit": "Without the Smepmp extension, it is not possible for a PMP rule to be enforced only on non-Machine m..."
  * "norm:smmpm_definition": "A machine-level extension that provides pointer masking for M-mode."
  * "norm:smnpm_definition": "A machine-level extension that provides pointer masking for the next lower privilege mode (S/HS if S..."
  * "norm:smstateen_hypervisor_rv64_csrs": "And if the hypervisor extension is implemented, another set of CSRs is added: hstateen0, hstateen1, ..."
  * "norm:smstateen_illegal_state_access": "Just
as with the counteren CSRs, when a stateen CSR prevents access to state by
less-privileged leve..."
  * "norm:smstateen_implicit_state_update": "When a stateen CSR prevents access to state for a privilege mode, attempting to execute in that priv..."
  * "norm:smstateen_mmode_rv64_csrs": "For RV64 harts, this extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State ..."
  * "norm:smstateen_rv32_upper_bits_csrs": "For RV32, there are CSR addresses for accessing the upper 32 bits of corresponding machine-level and..."
  * "norm:smstateen_smode_rv64_csrs": "If supervisor mode is implemented, another four CSRs are defined at supervisor level: sstateen0, sst..."
  * "norm:ssccfg_hyp_m_s_vsireg_illegal": "* An attempt to access any vsireg* from M or S mode raises an illegal-instruction exception."
  * "norm:ssccfg_hyp_vs_access_sireg_conditional": "* An attempt from VS-mode to access any sireg* (really vsireg*) raises an illegal-instruction except..."
  * "norm:ssccfg_hyp_vs_or_vu_access_vsireg_illegal": "If the hypervisor (H) extension is also implemented, then as specified by extensions Smcsrind/Sscsri..."
  * "norm:ssccfg_illegal_scountinhibit_cde0": "When menvcfg.CDE=0, attempts to access scountinhibit raise an illegal-instruction exception."
  * "norm:ssccfg_illegal_scountinhibit_vs_vu": "When Supervisor Counter Delegation
is enabled, attempts to access scountinhibit from VS-mode or VU-m..."
  * "norm:ssccfg_illegal_sireg3_6": "* attempts to access sireg3 or sireg6;"
  * "norm:ssccfg_illegal_sireg4_5_xlen64": "* attempts to access sireg4 or sireg5 when XLEN = 64;"
  * "norm:ssccfg_illegal_sireg_cde0": "* attempts to access any sireg* when menvcfg.CDE = 0;"
  * "norm:ssccfg_illegal_sireg_not_delegated": "* attempts to access sireg* when siselect = 0x41, or when the counter
selected by siselect is not de..."
  * "norm:ssccfg_lcofi_hvip_hvien": "For implementations that support Smcdeleg/Ssccfg, Sscofpmf, Smaia/Ssaia, and the H extension, the LC..."
  * "norm:ssccfg_lcofi_mvip_mvien": "For implementations that support Smcdeleg, Sscofpmf, and Smaia, the local-counter-overflow interrupt..."
  * "norm:ssccfg_missing_extension_illegal": "If any extension upon which the underlying state depends is not implemented, an attempt from M or S ..."
  * "norm:ssccfg_scountinhibit_delegated_rw": "For counters delegated to S-mode, the associated mcountinhibit bits can be accessed via scountinhibi..."
  * "norm:ssccfg_scountinhibit_exists": "Smcdeleg/Ssccfg defines a new scountinhibit register, a masked alias of mcountinhibit."
  * "norm:ssccfg_scountinhibit_nondelegated_ro": "For counters not delegated to S-mode, the associated bits in scountinhibit are read-only zero."
  * "norm:ssccfg_virtual_scountovf_vs_vu": "For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H extension, when menvcfg.CDE=1,..."
  * "norm:sscsrind_csrs_access_control": "If extension Smstateen is implemented together with Smcsrind, bit 60 of
state-enable register mstate..."
  * "norm:sscsrind_smode_csrs_sz": "Note that the widths of siselect and sireg* are always the current XLEN rather than SXLEN. Hence, fo..."
  * "norm:sscsrind_virtual_inst_fault": "A virtual-instruction  exception is raised for attempts from VS-mode or VU-mode to directly access v..."
  * "norm:sscsrind_vsmode_csrs_sz": "Like siselect and sireg*, the widths of vsiselect and vsireg* are always the current XLEN rather tha..."
  * "norm:ssnpm_definition": "A supervisor-level extension that provides pointer masking for the next lower privilege mode (U-mode..."
  * "norm:sspm_definition": "An extension that indicates that there is pointer-masking support available in supervisor mode, with..."
  * "norm:sstateen_bit_allocation": "The intention is to allocate the
bits of sstateen CSRs starting at the least-significant end, bit 0,..."
  * "norm:sstateen_bit_correspondence": "For every bit with a defined purpose in an sstateen CSR, the same bit is
defined in the matching mst..."
  * "norm:sstateen_encroachment_bits_roz": "In that case, the bit positions of "encroaching" bits will remain
forever read-only zeros in the mat..."
  * "norm:sstateen_ro1_bits": "A bit in a supervisor-level sstateen CSR cannot be read-only one unless the
same bit is read-only on..."
  * "norm:sstateen_user_access_control": "Each bit of a supervisor-level sstateen CSR controls user-level access (from
U-mode or VU-mode) to a..."
  * "norm:sstateen_vsmode_access_roz": "For every
bit in an hstateen CSR that is zero (whether read-only zero or set to zero),
the same bit ..."
  * "norm:sstc_purpose": "This extension serves to provide supervisor mode with its own CSR-based timer
interrupt facility tha..."
  * "norm:sstc_vs_facility": "Further, this extension adds a similar facility to the Hypervisor
extension for VS-mode."
  * "norm:stateen-reserved_roz": "Likewise, all reserved bits not
yet given a defined meaning are also read-only zeros."
  * "norm:stateen0-c_op": "The C bit controls access to any and all custom state."
  * "norm:stateen0-fcsr0_misa-f0_illegal_fpu_instr": "For convenience, when the stateen CSRs are implemented and
misa.F = 0, then if the FCSR bit of a con..."
  * "norm:stateen0-fcsr_op": "The FCSR bit controls access to fcsr for the case when floating-point
instructions operate on x regi..."
  * "norm:stateen0-jvt_op": "The JVT bit controls access to the jvt CSR provided by the Zcmt extension."
  * "norm:stateen_op": "The stateen registers at each level control access to state at all
less-privileged levels, but not a..."
  * "norm:stateen_unimplemented_state_roz": "Bits in any stateen CSR that are defined to control state that a hart doesn't
implement are read-onl..."
  * "norm:stateen_warl_access": "Each standard-defined bit of a stateen CSR is WARL and may be read-only zero or one, subject to the ..."
  * "norm:stce_bit_exist": "This extension adds the STCE bit to the menvcfg
(<<sec:menvcfg>>) and henvcfg
(<<s..."
  * "norm:stimecmp_exist": "This extension adds the S-level stimecmp
CSR (<<stimecmp>>)"
  * "norm:supm_definition": "An extension that indicates that there is pointer-masking support available in user mode, with some ..."
  * "norm:time_csr_architectural_availability": "Implementations can convert reads of the time and timeh CSRs into
loads to the memory-mapped mtime r..."
  * "norm:transition_counting_defined": "Further, the following defines how transitions between a non-inhibited privilege mode and an inhibit..."
  * "norm:unimplemented_mode_bits": "For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zer..."
  * "norm:vs_stage_speculative_a_bit": "when vsatp is active, VS-stage
page-table entries’ A bits must not be set as a result of speculative..."
  * "norm:vscause_wlrl": "vscause is a WLRL register that must be able to hold the same set of values that scause can hold."
  * "norm:vsireg_access_behaviour": "Ordinarily, each vsireg`i will access register state, access read-only 0 state, or raise an exceptio..."
  * "norm:vsireg_access_on_legal_vsiselect": "Otherwise, while vsiselect holds a number in a standard-defined and implemented range, attempts to a..."
  * "norm:vsiselect-msb_op": "Values of vsiselect with the most-significant bit set (bit XLEN - 1 = 1) are designated only for cus..."
  * "norm:vsiselect_min_range": "The vsiselect register will support the value range 0..0xFFF at a
minimum."
  * "norm:vsmode_virtual_inst_fault": "When `vsiselect holds a value that is implemented at HS level but not at VS level, attempts to acces..."
  * "norm:vstimecmp_exist": "and the VS-level vstimecmp CSR (<<vstimecmp>>)."

Deleted 9 tags:
  * "norm:satp-ppn_sv39_sv48_sv57_sz": "44-bit PPN"
  * "norm:vscause_warl": "vscause is a WLRL register that must be able to hold the same set of values that scause can hold."
  * "norm:zicflip_exception_priority": "The software-check exception caused by Zicfilp has higher priority than an illegal-instruction excep..."
  * "norm:zicflip_forward_trap_async_exception": "Synchronous exceptions with priority higher than that of a software-check
exception with xtval set t..."
  * "norm:zicflip_forward_trap_async_interrupt": "Asynchronous interrupts."
  * "norm:zicflip_forward_traps": "A trap may need to be delivered to the same or to a higher privilege mode upon
completion of JALR/C...."
  * "norm:zicflip_pelp_debug_mode": "Upon entry into Debug Mode, the pelp bit in dcsr is updated with the ELP at the privilege level the ..."
  * "norm:zicflip_pelp_trap": "When a trap is taken into privilege mode x, the xPELP is set to ELP and ELP is set to NO_LP_EXPECTED..."
  * "norm:zicflip_pelp_trap_return": "An MRET or SRET instruction is used to return from a trap in M-mode or S-mode, respectively.  When e..."

Modified 2 tags:
  * "norm:Zicsr_access":
      Reference: "The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR."
      Current:   "The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR, with the pat..."
  * "norm:misa_extensions_enc_tbl":
      Reference: "Bit|Character|Description
===
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25|A
..."
      Current:   "Bit|Character|Description
===
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25|A
..."

================================================================================
Summary: 333 total changes
  Added:    322
  Deleted:  9
  Modified: 2
================================================================================

---

What happens next:

• This comment is informational only and does not block merging
• When this PR is merged, a GitHub issue will be automatically created with the NormRules label for CSC tracking
• If these changes are unintentional, please update the PR before merging

How to update reference files (if needed):

make build-tags
cp build/riscv-unprivileged-norm-tags.json ref/
cp build/riscv-privileged-norm-tags.json ref/
git add ref/
git commit -m "Update normative tag reference files"

Note: New tags (additions) are automatically added to the reference files when PRs are merged to main. Only modifications and deletions require manual review.

This comment was automatically generated by the normative tag check workflow.

[eckhard-delfs-qualcomm]

Resolved after clarification.