Clarify sip can contain machine interrupts even though diagram shows 0s

[David Harris (davidharrishmc)]

Clarify the explanation regarding MEI, MTI, and MSI in the context of registers sip and sie.

[github-actions]

Normative Rule Changes Detected

This PR modifies normatively tagged text. Please review the changes below to ensure they are intentional.

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Normative Tag Change Report

riscv-spec Specification

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Tag Changes Report
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Reference file: ref/riscv-spec-norm-tags.json
Current file: build/riscv-spec-norm-tags.json
Modified 3 tags:
  * "norm:Zawrs_wrs-sto_stall_duration":
      Reference: "insn:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insn:wrs.nto[] but bounds the st..."
      Current:   "insn:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insn:wrs.nto[] but bounds the st..."
  * "norm:pm_uxl_clear":
      Reference: "Setting UXL/SXL/MXL to 1 will clear the corresponding pointer masking configuration bits."
      Current:   "Setting UXL/SXL to 1 will clear the corresponding pointer masking configuration bits."
  * "norm:sip_sie_bits_sz":
      Reference: "The standard portions (bits 15:0) of registers sip and sie are formatted as shown in Figures  and  r..."
      Current:   "The standard portions (bits 15:0) of registers sip and sie are formatted as shown in Figures  and  r..."

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Summary: 3 total changes
  Added:    0
  Deleted:  0
  Modified: 3
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[Andrew Waterman (aswaterman)]

This is true, but I don't think it's how it should be exposed in the supervisor spec. They're effectively custom interrupts at this level, rather than well-defined standard ones. I'll think about it and revisit this later.