Instruction indexes

[Bill Traynor (wmat)]

Andrew Waterman (@aswaterman) here is the instruction indexes for unpriv_rv32, unpriv_rv64, priv_rv32, and priv_rv64. The 4 new adoc files were created from all_instructions.adoc in UDB. I have a PR to add the script that creates them to riscv-unified-db. Currently these are manually created, however, it could be automated and synced to riscv-isa-manual with a GH action.

Please review the indexes in the PDFs and HTML before merging.

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Normative Rule Changes Detected

This PR modifies normatively tagged text. Please review the changes below to ensure they are intentional.

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Normative Tag Change Report

riscv-spec Specification

================================================================================
Tag Changes Report
================================================================================

Reference file: ref/riscv-spec-norm-tags.json
Current file: build/riscv-spec-norm-tags.json
Deleted 2 tags:
  * "norm:pm_family_extensions": "Pointer masking refers to a number of separate extensions, all of which are privileged."
  * "norm:pm_tag_check_impl": "The tag checks themselves can be implemented in software or hardware."

Modified 446 tags:
  * "norm:NTL-ALL_enc":
      Reference: "insn:ntl.all[] is encoded as insn:add[x0,x0,x5]."
      Current:   "insnlink:ntl.all[] is encoded as insnlink:add[x0,x0,x5]."
  * "norm:NTL-ALL_op":
      Reference: "The insn:ntl.all[] instruction indicates that the target instruction does not
exhibit temporal local..."
      Current:   "The insnlink:ntl.all[] instruction indicates that the target instruction does not
exhibit temporal l..."
  * "norm:NTL-LR_SC_exception":
      Reference: "Since the insn:ntl[] instructions are encoded as insn:add[]s, they can be used within LR/SC loops wi..."
      Current:   "Since the insn:ntl[] instructions are encoded as insnadds, they can be used within LR/SC loops witho..."
  * "norm:NTL-P1_enc":
      Reference: "insn:ntl.p1[] is encoded as
insn:add[x0,x0,x2]."
      Current:   "insnlink:ntl.p1[] is encoded as
insnlink:add[x0,x0,x2]."
  * "norm:NTL-P1_op":
      Reference: "The insn:ntl.p1[] instruction indicates that the target instruction does not
exhibit temporal locali..."
      Current:   "The insnlink:ntl.p1[] instruction indicates that the target instruction does not
exhibit temporal lo..."
  * "norm:NTL-PALL_enc":
      Reference: "insn:ntl.pall[] is encoded as insn:add[x0,x0,x3]."
      Current:   "insnlink:ntl.pall[] is encoded as insnlink:add[x0,x0,x3]."
  * "norm:NTL-PALL_op":
      Reference: "The insn:ntl.pall[] instruction indicates that the target instruction does not
exhibit temporal loca..."
      Current:   "The insnlink:ntl.pall[] instruction indicates that the target instruction does not
exhibit temporal ..."
  * "norm:NTL-S1_enc":
      Reference: "insn:ntl.s1[] is encoded as
insn:add[x0,x0,x4]."
      Current:   "insnlink:ntl.s1[] is encoded as
insnlink:add[x0,x0,x4]."
  * "norm:NTL-S1_op":
      Reference: "The insn:ntl.s1[] instruction indicates that the target instruction does not
exhibit temporal locali..."
      Current:   "The insnlink:ntl.s1[] instruction indicates that the target instruction does not
exhibit temporal lo..."
  * "norm:NTL-compressed_variants":
      Reference: "If the ext:c[] or ext:zca[] extension is provided, compressed variants of these HINTs are
also provi..."
      Current:   "If the ext:c[] or ext:zca[] extension is provided, compressed variants of these HINTs are
also provi..."
  * "norm:Zacas_rv32_amocas-d_op":
      Reference: "For RV32, insn:amocas.d[] atomically loads 64-bits of a data value from address in
rs1, compares the..."
      Current:   "For RV32, insnlink:amocas.d[] atomically loads 64-bits of a data value from address in
rs1, compares..."
  * "norm:Zacas_rv32_amocas-w_op":
      Reference: "For RV32, insn:amocas.w[] atomically loads a 32-bit data value from address in rs1,
compares the loa..."
      Current:   "For RV32, insnlink:amocas.w[] atomically loads a 32-bit data value from address in rs1,
compares the..."
  * "norm:Zacas_rv64_amocas-d_op":
      Reference: "For RV64, insn:amocas.d[] atomically loads 64-bits of a data value from address in
rs1, compares the..."
      Current:   "For RV64, insnlink:amocas.d[] atomically loads 64-bits of a data value from address in
rs1, compares..."
  * "norm:Zacas_rv64_amocas-q_op":
      Reference: "insn:amocas.q[] (RV64 only) atomically loads 128-bits of a data value from address in
rs1, compares ..."
      Current:   "insnlink:amocas.q[] (RV64 only) atomically loads 128-bits of a data value from address in
rs1, compa..."
  * "norm:Zacas_rv64_amocas-w_op":
      Reference: "For RV64, insn:amocas.w[] atomically loads a 32-bit data value from address in
rs1, compares the loa..."
      Current:   "For RV64, insnlink:amocas.w[] atomically loads a 32-bit data value from address in
rs1, compares the..."
  * "norm:Zawrs_exec_resume_rules":
      Reference: "insn:wrs.nto[] and insn:wrs.sto[] instructions follow the rules of the insn:wfi[] instruction
for re..."
      Current:   "insnlink:wrs.nto[] and insnlink:wrs.sto[] instructions follow the rules of the insnlink:wfi[] instru..."
  * "norm:Zawrs_priv_illegal_instr_excp":
      Reference: "When the csr::[tw] (timeout wait) bit in csr:mstatus[] is set and insn:wrs.nto[] is executed
in any ..."
      Current:   "When the csr::[tw] (timeout wait) bit in csr:mstatus[] is set and insnlink:wrs.nto[] is executed
in ..."
  * "norm:Zawrs_virtual_instr_excp":
      Reference: "When executing in VS- or VU-mode, if the csr::[vtw] bit is set in csr:hstatus[], the
csr::[tw] bit i..."
      Current:   "When executing in VS- or VU-mode, if the csr::[vtw] bit is set in csr:hstatus[], the
csr::[tw] bit i..."
  * "norm:Zawrs_wrs-nto_stall_exec":
      Reference: "Then a subsequent insn:wrs.nto[] instruction would cause the hart to temporarily
stall execution in ..."
      Current:   "Then a subsequent insnlink:wrs.nto[] instruction would cause the hart to temporarily
stall execution..."
  * "norm:Zawrs_wrs-sto_stall_duration":
      Reference: "insn:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insn:wrs.nto[] but bounds the st..."
      Current:   "insnlink:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insnlink:wrs.nto[] but bound..."
  * "norm:Zcmop_enc":
      Reference: "insn:c.mop.n[] is encoded in the reserved encoding space
corresponding to insn:c.lui[xN,0], as shown..."
      Current:   "insn:c.mop.n[] is encoded in the reserved encoding space
corresponding to insnlink:c.lui[xN,0], as s..."
  * "norm:Zcmt_fetch":
      Reference: "For a table jump instruction, the table entry that the instruction selects is considered an extensio..."
      Current:   "For a table jump instruction, the table entry that the instruction selects is considered an extensio..."
  * "norm:Zdinx_D_instrs":
      Reference: "The ext:zdinx[] extension adds all of the instructions that the ext:d[] extension adds, except for t..."
      Current:   "The ext:zdinx[] extension adds all of the instructions that the ext:d[] extension adds, except for t..."
  * "norm:Zfhinxmin_instrs":
      Reference: "The ext:zhinxmin[] extension includes the following instructions from the ext:zhinx[] extension: ins..."
      Current:   "The ext:zhinxmin[] extension includes the following instructions from the ext:zhinx[] extension: ins..."
  * "norm:Zfinx_F_instrs":
      Reference: "The ext:zfinx[] extension adds all of the instructions that the ext:f[] extension adds, except for t..."
      Current:   "The ext:zfinx[] extension adds all of the instructions that the ext:f[] extension adds, except for t..."
  * "norm:Zhinx_Zfh_instrs":
      Reference: "The ext:zhinx[] extension adds all of the instructions that the ext:zfh[] extension adds, except for..."
      Current:   "The ext:zhinx[] extension adds all of the instructions that the ext:zfh[] extension adds, except for..."
  * "norm:Zicfilp_forward_traps":
      Reference: "A trap may need to be delivered to the same or to a higher privilege mode upon
completion of insn:ja..."
      Current:   "A trap may need to be delivered to the same or to a higher privilege mode upon
completion of insnlin..."
  * "norm:Zicfilp_pelp_trap_return":
      Reference: "An insn:mret[] or insn:sret[] instruction is used to return from a trap in M-mode or S-mode, respect..."
      Current:   "An insnmret or insnsret instruction is used to return from a trap in M-mode or S-mode, respectively...."
  * "norm:Zilsd_RVWMO_exc_misaligned":
      Reference: "For the purposes of RVWMO and exception handling, insn:ld[] and insn:sd[] instructions are
considere..."
      Current:   "For the purposes of RVWMO and exception handling, insnlink:ld[] and insnlink:sd[] instructions are
c..."
  * "norm:Zilsd_align4_two_4byte":
      Reference: "an insn:ld[] or insn:sd[] instruction whose effective address is a multiple of 4 gives rise
to two 4..."
      Current:   "an insnlink:ld[] or insnlink:sd[] instruction whose effective address is a multiple of 4 gives rise
..."
  * "norm:Zilsd_c-ldsp_op":
      Reference: "Loads stack-pointer relative 64-bit value into registers rd' and rd'+1. It computes its effective ad..."
      Current:   "Loads stack-pointer relative 64-bit value into registers rd' and rd'+1. It computes its effective ad..."
  * "norm:Zilsd_c-ldsp_x0":
      Reference: "For insn:c.ldsp[], usage of x0 as the destination is reserved."
      Current:   "For insnlink:c.ldsp[], usage of x0 as the destination is reserved."
  * "norm:Zilsd_c-sd_op":
      Reference: "Stores a 64-bit value from registers rs2' and rs2'+1. It computes an effective address by adding the..."
      Current:   "Stores a 64-bit value from registers rs2' and rs2'+1. It computes an effective address by adding the..."
  * "norm:Zilsd_c-sdsp_op":
      Reference: "Stores a stack-pointer relative 64-bit value from registers rs2' and rs2'+1. It computes an effectiv..."
      Current:   "Stores a stack-pointer relative 64-bit value from registers rs2' and rs2'+1. It computes an effectiv..."
  * "norm:Zilsd_sd_x0":
      Reference: "If using x0 as src of insn:sd[], the entire 64-bit operand is zero — i.e., register x1 is not access..."
      Current:   "If using x0 as src of insnsd, the entire 64-bit operand is zero — i.e., register x1 is not accessed."
  * "norm:Zve64_eew64_nsupport_vmulh":
      Reference: "ext:zve64x[] supports all vector integer instructions
(<<sec-vector-integer>>), except t..."
      Current:   "ext:zve64x[] supports all vector integer instructions
(<<sec-vector-integer>>), except t..."
  * "norm:Zve64_eew64_nsupport_vsmul":
      Reference: "ext:zve64x[] supports all vector fixed-point arithmetic
instructions (<<sec-vector-fixed-point..."
      Current:   "ext:zve64x[] supports all vector fixed-point arithmetic
instructions (<<sec-vector-fixed-point..."
  * "norm:Zvfh_instr_cvt":
      Reference: "Additionally, conversions between 8-bit integers and binary16 values are
provided.  The floating-poi..."
      Current:   "Additionally, conversions between 8-bit integers and binary16 values are
provided.  The floating-poi..."
  * "norm:a_domain_specific_ordering":
      Reference: "The bits
order accesses to one of the two address domains, memory or I/O,
depending on which address..."
      Current:   "The bits
order accesses to one of the two address domains, memory or I/O,
depending on which address..."
  * "norm:add_op":
      Reference: "insn:add[] performs the addition of rs1 and rs2."
      Current:   "insnlink:add[] performs the addition of rs1 and rs2."
  * "norm:addi_op":
      Reference: "insn:addi[] adds the sign-extended 12-bit immediate to register rs1."
      Current:   "insnlink:addi[] adds the sign-extended 12-bit immediate to register rs1."
  * "norm:addiw_op":
      Reference: "insn:addiw[] is an RV64I instruction that adds the sign-extended 12-bit
immediate to register rs1 an..."
      Current:   "insnlink:addiw[] is an RV64I instruction that adds the sign-extended 12-bit
immediate to register rs..."
  * "norm:addw_subw_op":
      Reference: "insn:addw[] and insn:subw[] are RV64I-only instructions that are defined analogously
to insn:add[] a..."
      Current:   "insnlink:addw[] and insnlink:subw[] are RV64I-only instructions that are defined analogously
to insn..."
  * "norm:and_or_xor_op":
      Reference: "insn:and[], insn:or[], and insn:xor[] perform bitwise logical operations."
      Current:   "insnlink:and[], insnlink:or[], and insnlink:xor[] perform bitwise logical operations."
  * "norm:andi_ori_xori_op":
      Reference: "insn:andi[], insn:ori[], insn:xori[] are logical operations that perform bitwise AND, OR, and
XOR on..."
      Current:   "insnlink:andi[], insnlink:ori[], insnlink:xori[] are logical operations that perform bitwise AND, OR..."
  * "norm:auipc_op":
      Reference: "insn:auipc[] forms a 32-bit offset from
the U-immediate, filling in the lowest 12 bits with zeros, a..."
      Current:   "insnlink:auipc[] forms a 32-bit offset from
the U-immediate, filling in the lowest 12 bits with zero..."
  * "norm:auipc_op_rv64i":
      Reference: "insn:auipc[] forms a 32-bit offset from the U-immediate, filling in the lowest
12 bits with zeros, s..."
      Current:   "insnlink:auipc[] forms a 32-bit offset from the U-immediate, filling in the lowest
12 bits with zero..."
  * "norm:beq_bne_op":
      Reference: "insn:beq[] and insn:bne[] take the branch if registers rs1 and rs2 are equal or unequal respectively..."
      Current:   "insnlink:beq[] and insnlink:bne[] take the branch if registers rs1 and rs2 are equal or unequal resp..."
  * "norm:bge_bgeu_op":
      Reference: "insn:bge[] and insn:bgeu[] take the branch if rs1 is greater than or equal to rs2,
using signed and ..."
      Current:   "insnlink:bge[] and insnlink:bgeu[] take the branch if rs1 is greater than or equal to rs2,
using sig..."
  * "norm:blt_bltu_op":
      Reference: "insn:blt[] and insn:bltu[] take the branch if rs1 is less than rs2, using signed and
unsigned compar..."
      Current:   "insnlink:blt[] and insnlink:bltu[] take the branch if rs1 is less than rs2, using signed and
unsigne..."
  * "norm:c-add_op":
      Reference: "insn:c.add[] adds the values in registers rd and rs2 and writes the result
to register rd. It expand..."
      Current:   "insnlink:c.add[] adds the values in registers rd and rs2 and writes the result
to register rd. It ex..."
  * "norm:c-add_val":
      Reference: "insn:c.add[] is only
valid when rs2≠x0; the code points with rs2=x0 correspond to the
insn:c.jalr[] ..."
      Current:   "insnlink:c.add[] is only
valid when rs2≠x0; the code points with rs2=x0 correspond to the
insnlink:c..."
  * "norm:c-addi16sp_op":
      Reference: "insn:c.addi16sp[] (add immediate to stack pointer)
shares the opcode with insn:c.lui[], but has a de..."
      Current:   "insnlink:c.addi16sp[] (add immediate to stack pointer)
shares the opcode with insnlink:c.lui[], but ..."
  * "norm:c-addi16sp_rsv":
      Reference: "insn:c.addi16sp[] is valid only when
nzimm≠0; the code point with nzimm=0 is reserved."
      Current:   "insnlink:c.addi16sp[] is valid only when
nzimm≠0; the code point with nzimm=0 is reserved."
  * "norm:c-addi4spn_op":
      Reference: "insn:c.addi4spn[] (add immediate to stack pointer, non-destructive)
is a CIW-format instruction that..."
      Current:   "insnlink:c.addi4spn[] (add immediate to stack pointer, non-destructive)
is a CIW-format instruction ..."
  * "norm:c-addi4spn_rsv":
      Reference: "insn:c.addi4spn[] is valid only when
nzuimm≠0; the code points with nzuimm=0 are
reserved."
      Current:   "insnlink:c.addi4spn[] is valid only when
nzuimm≠0; the code points with nzuimm=0 are
reserved."
  * "norm:c-addi_nop":
      Reference: "The code points with rd=x0 encode the insn:c.nop[] instruction, of
which the code points with imm≠0 ..."
      Current:   "The code points with rd=x0 encode the insnlink:c.nop[] instruction, of
which the code points with im..."
  * "norm:c-addi_op":
      Reference: "insn:c.addi[] adds the non-zero sign-extended 6-bit immediate to the value in
register rd then write..."
      Current:   "insnlink:c.addi[] adds the non-zero sign-extended 6-bit immediate to the value in
register rd then w..."
  * "norm:c-addiw_op":
      Reference: "insn:c.addiw[] is an XLEN=64-only instruction that performs the same
computation but produces a 32-b..."
      Current:   "insnlink:c.addiw[] is an XLEN=64-only instruction that performs the same
computation but produces a ..."
  * "norm:c-addiw_rsv":
      Reference: "insn:c.addiw[] is
valid only when rd≠x0; the code points with
rd=x0 are reserved."
      Current:   "insnlink:c.addiw[] is
valid only when rd≠x0; the code points with
rd=x0 are reserved."
  * "norm:c-addw_op":
      Reference: "insn:c.addw[] is an XLEN=64-only instruction that adds the values in
registers rd′ and rs2′, then
si..."
      Current:   "insnlink:c.addw[] is an XLEN=64-only instruction that adds the values in
registers rd′ and rs2′, the..."
  * "norm:c-and_op":
      Reference: "insn:c.and[] computes the bitwise AND of the values in registers
rd′ and rs2′, then writes the resul..."
      Current:   "insnlink:c.and[] computes the bitwise AND of the values in registers
rd′ and rs2′, then writes the r..."
  * "norm:c-andi_op":
      Reference: "insn:c.andi[] is a CB-format instruction that computes the bitwise AND of the
value in register rd′ ..."
      Current:   "insnlink:c.andi[] is a CB-format instruction that computes the bitwise AND of the
value in register ..."
  * "norm:c-beqz_op":
      Reference: "insn:c.beqz[] performs conditional control transfers. The offset is
sign-extended and added to the p..."
      Current:   "insnlink:c.beqz[] performs conditional control transfers. The offset is
sign-extended and added to t..."
  * "norm:c-bnez_op":
      Reference: "insn:c.bnez[] is defined analogously, but it takes the branch if
rs1′ contains a nonzero value. It e..."
      Current:   "insnlink:c.bnez[] is defined analogously, but it takes the branch if
rs1′ contains a nonzero value. ..."
  * "norm:c-ebreak_op":
      Reference: "Debuggers can use the insn:c.ebreak[] instruction, which expands to insn:ebreak[],
to cause control ..."
      Current:   "Debuggers can use the insnlink:c.ebreak[] instruction, which expands to insnlink:ebreak[],
to cause ..."
  * "norm:c-fld_op":
      Reference: "insn:c.fld[] is an RV32DC/RV64DC-only instruction that loads a double-precision
floating-point value..."
      Current:   "insnlink:c.fld[] is an RV32DC/RV64DC-only instruction that loads a double-precision
floating-point v..."
  * "norm:c-fldsp_op":
      Reference: "insn:c.fldsp[] is an RV32DC/RV64DC-only instruction that loads a
double-precision floating-point val..."
      Current:   "insnlink:c.fldsp[] is an RV32DC/RV64DC-only instruction that loads a
double-precision floating-point..."
  * "norm:c-flw_op":
      Reference: "insn:c.flw[] is an RV32FC-only instruction that loads a single-precision
floating-point value from m..."
      Current:   "insnlink:c.flw[] is an RV32FC-only instruction that loads a single-precision
floating-point value fr..."
  * "norm:c-flwsp_op":
      Reference: "insn:c.flwsp[] is an RV32FC-only instruction that loads a single-precision
floating-point value from..."
      Current:   "insnlink:c.flwsp[] is an RV32FC-only instruction that loads a single-precision
floating-point value ..."
  * "norm:c-fsd_op":
      Reference: "insn:c.fsd[] is an RV32DC/RV64DC-only instruction that stores a
double-precision floating-point valu..."
      Current:   "insnlink:c.fsd[] is an RV32DC/RV64DC-only instruction that stores a
double-precision floating-point ..."
  * "norm:c-fsdwsp_op":
      Reference: "insn:c.fsdsp[] is an RV32DC/RV64DC-only instruction that stores a
double-precision floating-point va..."
      Current:   "insnlink:c.fsdsp[] is an RV32DC/RV64DC-only instruction that stores a
double-precision floating-poin..."
  * "norm:c-fsw_op":
      Reference: "insn:c.fsw[] is an RV32FC-only instruction that stores a single-precision
floating-point value in fl..."
      Current:   "insnlink:c.fsw[] is an RV32FC-only instruction that stores a single-precision
floating-point value i..."
  * "norm:c-fswsp_op":
      Reference: "insn:c.fswsp[] is an RV32FC-only instruction that stores a single-precision
floating-point value in ..."
      Current:   "insnlink:c.fswsp[] is an RV32FC-only instruction that stores a single-precision
floating-point value..."
  * "norm:c-j_op":
      Reference: "insn:c.j[] performs an unconditional control transfer. The offset is
sign-extended and added to the ..."
      Current:   "insnlink:c.j[] performs an unconditional control transfer. The offset is
sign-extended and added to ..."
  * "norm:c-jal_op":
      Reference: "insn:c.jal[] is an XLEN=32-only instruction that performs the same operation as
insn:c.j[], but addi..."
      Current:   "insnlink:c.jal[] is an XLEN=32-only instruction that performs the same operation as
insnlink:c.j[], ..."
  * "norm:c-jalr_ebreak":
      Reference: "insn:c.jalr[] is valid only when
rs1≠x0; the code point with
rs1=x0 corresponds to the insn:c.ebreak..."
      Current:   "insnlink:c.jalr[] is valid only when
rs1≠x0; the code point with
rs1=x0 corresponds to the insnlink:..."
  * "norm:c-jalr_op":
      Reference: "insn:c.jalr[] (jump and link register) performs the same operation as insn:c.jr[], but
additionally ..."
      Current:   "insnlink:c.jalr[] (jump and link register) performs the same operation as insnlink:c.jr[], but
addit..."
  * "norm:c-jr_op":
      Reference: "insn:c.jr[] (jump register) performs an unconditional control transfer to the
address in register rs..."
      Current:   "insnlink:c.jr[] (jump register) performs an unconditional control transfer to the
address in registe..."
  * "norm:c-jr_rsv":
      Reference: "insn:c.jr[] is
valid only when rs1≠x0; the code
point with rs1=x0 is reserved."
      Current:   "insnlink:c.jr[] is
valid only when rs1≠x0; the code
point with rs1=x0 is reserved."
  * "norm:c-ld_op":
      Reference: "insn:c.ld[] is an XLEN=64-only instruction that loads a 64-bit value from
memory into register rd′. ..."
      Current:   "insnlink:c.ld[] is an XLEN=64-only instruction that loads a 64-bit value from
memory into register r..."
  * "norm:c-ldsp_op":
      Reference: "insn:c.ldsp[] is an XLEN=64-only instruction that loads a 64-bit value
from memory into register rd...."
      Current:   "insnlink:c.ldsp[] is an XLEN=64-only instruction that loads a 64-bit value
from memory into register..."
  * "norm:c-ldsp_rsv":
      Reference: "insn:c.ldsp[] is valid only when
rd≠x0; the code points with
rd=x0 are reserved."
      Current:   "insnlink:c.ldsp[] is valid only when
rd≠x0; the code points with
rd=x0 are reserved."
  * "norm:c-li_hint":
      Reference: "The insn:c.li[] code points with rd=x0 are HINTs."
      Current:   "The insnlink:c.li[] code points with rd=x0 are HINTs."
  * "norm:c-li_op":
      Reference: "insn:c.li[] loads the sign-extended 6-bit immediate, imm, into register rd.
It expands into insn:add..."
      Current:   "insnlink:c.li[] loads the sign-extended 6-bit immediate, imm, into register rd.
It expands into insn..."
  * "norm:c-lui_op":
      Reference: "insn:c.lui[] loads the non-zero 6-bit immediate field into bits 17–12 of the
destination register, c..."
      Current:   "insnlink:c.lui[] loads the non-zero 6-bit immediate field into bits 17–12 of the
destination registe..."
  * "norm:c-lui_rsv":
      Reference: "insn:c.lui[] is valid only when
rd≠x2,
and when the immediate is not equal to zero. The code points ..."
      Current:   "insnlink:c.lui[] is valid only when
rd≠x2,
and when the immediate is not equal to zero. The code poi..."
  * "norm:c-lw_op":
      Reference: "insn:c.lw[] loads a 32-bit value from memory into register
rd′. It computes an effective address by ..."
      Current:   "insnlink:c.lw[] loads a 32-bit value from memory into register
rd′. It computes an effective address..."
  * "norm:c-lwsp_op":
      Reference: "insn:c.lwsp[] loads a 32-bit value from memory into register rd. It computes
an effective address by..."
      Current:   "insnlink:c.lwsp[] loads a 32-bit value from memory into register rd. It computes
an effective addres..."
  * "norm:c-lwsp_rsv":
      Reference: "insn:c.lwsp[] is
valid only when rd≠x0; the code points with rd=x0 are reserved."
      Current:   "insnlink:c.lwsp[] is
valid only when rd≠x0; the code points with rd=x0 are reserved."
  * "norm:c-mv_jr":
      Reference: "insn:c.mv[] is valid only when
rs2≠x0; the code points with rs2=x0 correspond to the insn:c.jr[] ins..."
      Current:   "insnlink:c.mv[] is valid only when
rs2≠x0; the code points with rs2=x0 correspond to the insnlink:c...."
  * "norm:c-mv_op":
      Reference: "insn:c.mv[] copies the value in register rs2 into register rd. It expands
into insn:add[rd,x0,rs2]."
      Current:   "insnlink:c.mv[] copies the value in register rs2 into register rd. It expands
into insnlink:add[rd,x..."
  * "norm:c-nop_hint":
      Reference: "The insn:c.nop[] code points
with imm≠0 encode HINTs."
      Current:   "The insnlink:c.nop[] code points
with imm≠0 encode HINTs."
  * "norm:c-nop_op":
      Reference: "insn:c.nop[] is a CI-format instruction that does not change any user-visible
state, except for adva..."
      Current:   "insnlink:c.nop[] is a CI-format instruction that does not change any user-visible
state, except for ..."
  * "norm:c-or_op":
      Reference: "insn:c.or[] computes the bitwise OR of the values in registers
rd′ and rs2′, then writes the result
..."
      Current:   "insnlink:c.or[] computes the bitwise OR of the values in registers
rd′ and rs2′, then writes the res..."
  * "norm:c-sd_op":
      Reference: "insn:c.sd[] is an XLEN=64-only instruction that stores a 64-bit value in
register rs2′ to memory. It..."
      Current:   "insnlink:c.sd[] is an XLEN=64-only instruction that stores a 64-bit value in
register rs2′ to memory..."
  * "norm:c-sdsp_op":
      Reference: "insn:c.sdsp[] is an XLEN=64-only instruction that stores a 64-bit value in
register rs2 to memory. I..."
      Current:   "insnlink:c.sdsp[] is an XLEN=64-only instruction that stores a 64-bit value in
register rs2 to memor..."
  * "norm:c-slli_hint":
      Reference: "The insn:c.slli[] code points with shamt=0 or with rd=x0 are HINTs."
      Current:   "The insnlink:c.slli[] code points with shamt=0 or with rd=x0 are HINTs."
  * "norm:c-slli_op":
      Reference: "insn:c.slli[] is a CI-format instruction that performs a logical left shift of
the value in register..."
      Current:   "insnlink:c.slli[] is a CI-format instruction that performs a logical left shift of
the value in regi..."
  * "norm:c-srai_op":
      Reference: "insn:c.srai[] is defined analogously to insn:c.srli[], but instead performs an
arithmetic right shif..."
      Current:   "insnlink:c.srai[] is defined analogously to insnlink:c.srli[], but instead performs an
arithmetic ri..."
  * "norm:c-srli_hint":
      Reference: "The insn:c.srli[] code points with shamt=0 are HINTs."
      Current:   "The insnlink:c.srli[] code points with shamt=0 are HINTs."
  * "norm:c-srli_op":
      Reference: "insn:c.srli[] is a CB-format instruction that performs a logical right shift of
the value in registe..."
      Current:   "insnlink:c.srli[] is a CB-format instruction that performs a logical right shift of
the value in reg..."
  * "norm:c-sub_op":
      Reference: "insn:c.sub[] subtracts the value in register rs2′ from the
value in register rd′, then writes the re..."
      Current:   "insnlink:c.sub[] subtracts the value in register rs2′ from the
value in register rd′, then writes th..."
  * "norm:c-subw_op":
      Reference: "insn:c.subw[] is an XLEN=64-only instruction that subtracts the value in
register rs2′ from the valu..."
      Current:   "insnlink:c.subw[] is an XLEN=64-only instruction that subtracts the value in
register rs2′ from the ..."
  * "norm:c-sw_op":
      Reference: "insn:c.sw[] stores a 32-bit value in register rs2′ to memory.
It computes an effective address by ad..."
      Current:   "insnlink:c.sw[] stores a 32-bit value in register rs2′ to memory.
It computes an effective address b..."
  * "norm:c-swsp_op":
      Reference: "insn:c.swsp[] stores a 32-bit value in register rs2 to memory. It computes an
effective address by a..."
      Current:   "insnlink:c.swsp[] stores a 32-bit value in register rs2 to memory. It computes an
effective address ..."
  * "norm:c-xor_op":
      Reference: "insn:c.xor[] computes the bitwise XOR of the values in registers
rd′ and rs2′, then writes the resul..."
      Current:   "insnlink:c.xor[] computes the bitwise XOR of the values in registers
rd′ and rs2′, then writes the r..."
  * "norm:cbo-clean_cbo-flush":
      Reference: "A insn:cbo.clean[] or insn:cbo.flush[] instruction executes or raises an illegal-instruction or virt..."
      Current:   "A insncbo.clean or insncbo.flush instruction executes or raises an illegal-instruction or virtual-in..."
  * "norm:cbo-clean_op":
      Reference: "A insn:cbo.clean[] instruction performs a clean operation on the cache block whose
effective address..."
      Current:   "A insnlink:cbo.clean[] instruction performs a clean operation on the cache block whose
effective add..."
  * "norm:cbo-flush_op":
      Reference: "A insn:cbo.flush[] instruction performs a flush operation on the cache block whose
that contains the..."
      Current:   "A insnlink:cbo.flush[] instruction performs a flush operation on the cache block whose
that contains..."
  * "norm:cbo-inval":
      Reference: "A insn:cbo.inval[] instruction executes or raises either an illegal-instruction exception or a virtu..."
      Current:   "A insncbo.inval instruction executes or raises either an illegal-instruction exception or a virtual-..."
  * "norm:cbo-inval_op":
      Reference: "A insn:cbo.inval[] instruction performs an invalidate operation on the cache block
that contains the..."
      Current:   "A insnlink:cbo.inval[] instruction performs an invalidate operation on the cache block
that contains..."
  * "norm:cbo-zero_basedon_xenvcfg-CBZE":
      Reference: "Finally, a insn:cbo.zero[] instruction executes or raises an illegal-instruction or virtual-instruct..."
      Current:   "Finally, a insncbo.zero instruction executes or raises an illegal-instruction or virtual-instruction..."
  * "norm:cbo-zero_op":
      Reference: "A insn:cbo.zero[] instruction performs stores of zeros to the full set of bytes
corresponding to the..."
      Current:   "A insnlink:cbo.zero[] instruction performs stores of zeros to the full set of bytes
corresponding to..."
  * "norm:cfi_call_term":
      Reference: "The term call is used to refer to a insn:jal[], insn:jalr[] or insn:c.jal[] instruction with a link ..."
      Current:   "The term call is used to refer to a insnjal, insnjalr or insnc.jal instruction with a link register ..."
  * "norm:cfi_indirect-jump_term":
      Reference: "The term indirect jump is used to refer to a insn:jalr[] instruction with rd=x0 and where the rs1 is..."
      Current:   "The term indirect jump is used to refer to a insnjalr instruction with rd=x0 and where the rs1 is no..."
  * "norm:cfi_return_term":
      Reference: "The term return is used to refer to a insn:jalr[] instruction with rd=x0 and with rs1=x1 or rs1=x5. ..."
      Current:   "The term return is used to refer to a insnjalr instruction with rd=x0 and with rs1=x1 or rs1=x5. A i..."
  * "norm:cm-jalt_op":
      Reference: "insn:cm.jalt[] reads an entry from the jump vector table in memory and jumps to the address that was..."
      Current:   "insnlink:cm.jalt[] reads an entry from the jump vector table in memory and jumps to the address that..."
  * "norm:cm-jt_op":
      Reference: "insn:cm.jt[] reads an entry from the jump vector table in memory and jumps to the address that was r..."
      Current:   "insnlink:cm.jt[] reads an entry from the jump vector table in memory and jumps to the address that w..."
  * "norm:constrained_lrsc_instruction_set":
      Reference: "An insn:lr[]/insn:sc[] sequence begins with an insn:lr[] instruction and ends with an
insn:sc[] inst..."
      Current:   "An insn:lr[]/insn:sc[] sequence begins with an insn:lr[] instruction and ends with an
insn:sc[] inst..."
  * "norm:csr_fence_ordering":
      Reference: "To enforce ordering in all
other cases, software should execute a insn:fence[] instruction between t..."
      Current:   "To enforce ordering in all
other cases, software should execute a insnlink:fence[] instruction betwe..."
  * "norm:csr_rs1_uimm_side_effect":
      Reference: "insn:csrrs[], insn:csrrsi[], insn:csrrc[], and insn:csrrci[]
only action side effects for fields for..."
      Current:   "insnlink:csrrs[], insnlink:csrrsi[], insnlink:csrrc[], and insnlink:csrrci[]
only action side effect..."
  * "norm:csrrc_op":
      Reference: "The insn:csrrc[] (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-ex..."
      Current:   "The insncsrrc (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-exten..."
  * "norm:csrrs_csrrc_rs1_x0":
      Reference: "For both insn:csrrs[] and insn:csrrc[], if rs1=x0, then the instruction will not write to the CSR at..."
      Current:   "For both insncsrrs and insncsrrc, if rs1=x0, then the instruction will not write to the CSR at all, ..."
  * "norm:csrrs_op":
      Reference: "The insn:csrrs[] (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-exte..."
      Current:   "The insncsrrs (Atomic Read and Set Bits in CSR) instruction reads the value of the CSR, zero-extends..."
  * "norm:csrrsi_csrrci_uimm_zero":
      Reference: "For insn:csrrsi[] and insn:csrrci[], if the uimm[4:0] field is zero, then these
instructions will no..."
      Current:   "For insnlink:csrrsi[] and insnlink:csrrci[], if the uimm[4:0] field is zero, then these
instructions..."
  * "norm:csrrw_op":
      Reference: "The insn:csrrw[] (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer..."
      Current:   "The insncsrrw (Atomic Read/Write CSR) instruction atomically swaps values in the CSRs and integer re..."
  * "norm:csrrw_rs1_x0":
      Reference: "A insn:csrrw[] with rs1=x0 will attempt to write zero to the destination CSR."
      Current:   "A insncsrrw with rs1=x0 will attempt to write zero to the destination CSR."
  * "norm:csrrwi_csrrsi_csrrci_ops":
      Reference: "The insn:csrrwi[], insn:csrrsi[], and insn:csrrci[] variants are similar to insn:csrrw[], insn:csrrs..."
      Current:   "The insncsrrwi, insncsrrsi, and insncsrrci variants are similar to insncsrrw, insncsrrs, and insncsr..."
  * "norm:csrrwi_rd_x0":
      Reference: "For
insn:csrrwi[], if rd=x0, then the instruction shall not read the CSR and
shall not cause any of ..."
      Current:   "For
insnlink:csrrwi[], if rd=x0, then the instruction shall not read the CSR and
shall not cause any..."
  * "norm:div_divu_op":
      Reference: "insn:div[] and insn:divu[] perform an XLEN bits by XLEN bits signed and unsigned
integer division of..."
      Current:   "insnlink:div[] and insnlink:divu[] perform an XLEN bits by XLEN bits signed and unsigned
integer div..."
  * "norm:divw_divuw_op":
      Reference: "insn:divw[] and insn:divuw[] are RV64 instructions that divide the lower 32 bits of
rs1 by the lower..."
      Current:   "insnlink:divw[] and insnlink:divuw[] are RV64 instructions that divide the lower 32 bits of
rs1 by t..."
  * "norm:ebreak_op1":
      Reference: "The insn:ebreak[] instruction is used to return control to a debugging environment."
      Current:   "The insnlink:ebreak[] instruction is used to return control to a debugging environment."
  * "norm:ecall_op1":
      Reference: "The insn:ecall[] instruction is used to make a service request to the execution environment."
      Current:   "The insnlink:ecall[] instruction is used to make a service request to the execution environment."
  * "norm:fadd-s_fmul-s_op":
      Reference: "insn:fadd.s[] and insn:fmul.s[] perform single-precision floating-point addition and multiplication ..."
      Current:   "insnlink:fadd.s[] and insnlink:fmul.s[] perform single-precision floating-point addition and multipl..."
  * "norm:fclass-d_op":
      Reference: "The double-precision floating-point classify instruction, insn:fclass.d[], is defined analogously to..."
      Current:   "The double-precision floating-point classify instruction, insnfclass.d, is defined analogously to it..."
  * "norm:fclass-h_op":
      Reference: "The half-precision floating-point classify instruction, insn:fclass.h[], is defined analogously to i..."
      Current:   "The half-precision floating-point classify instruction, insnfclass.h, is defined analogously to its ..."
  * "norm:fclass-q_op":
      Reference: "The quad-precision floating-point classify instruction, insn:fclass.q[], is defined analogously to i..."
      Current:   "The quad-precision floating-point classify instruction, insnfclass.q, is defined analogously to its ..."
  * "norm:fclass-s_op":
      Reference: "The insn:fclass.s[] instruction examines the value in floating-point register rs1 and writes to inte..."
      Current:   "The insnfclass.s instruction examines the value in floating-point register rs1 and writes to integer..."
  * "norm:fcvt-d-h_fcvt-h-d_op":
      Reference: "If the ext:d[] extension is present, insn:fcvt.d.h[] or insn:fcvt.h.d[] converts a half-precision fl..."
      Current:   "If the ext:d[] extension is present, insnlink:fcvt.d.h[] or insnlink:fcvt.h.d[] converts a half-prec..."
  * "norm:fcvt-d-q_fcvt-q-d_op":
      Reference: "insn:fcvt.d.q[] or insn:fcvt.q.d[] converts a quad-precision floating-point number to
a double-preci..."
      Current:   "insnlink:fcvt.d.q[] or insnlink:fcvt.q.d[] converts a quad-precision floating-point number to
a doub..."
  * "norm:fcvt-d-w_fcvt-d-l_op":
      Reference: "insn:fcvt.d.w[] or insn:fcvt.d.l[] converts a
32-bit or 64-bit signed integer, respectively, in inte..."
      Current:   "insnlink:fcvt.d.w[] or insnlink:fcvt.d.l[] converts a
32-bit or 64-bit signed integer, respectively,..."
  * "norm:fcvt-h-w_fcvt-h-l_op":
      Reference: "insn:fcvt.h.w[] or insn:fcvt.h.l[] converts a 32-bit or 64-bit signed integer, respectively, into a ..."
      Current:   "insnlink:fcvt.h.w[] or insnlink:fcvt.h.l[] converts a 32-bit or 64-bit signed integer, respectively,..."
  * "norm:fcvt-l-s_fcvt-w-s_op":
      Reference: "insn:fcvt.w.s[] or
insn:fcvt.l.s[] converts a floating-point number in floating-point register
rs1 t..."
      Current:   "insnlink:fcvt.w.s[] or
insnlink:fcvt.l.s[] converts a floating-point number in floating-point regist..."
  * "norm:fcvt-q-h_fcvt-h-q_op":
      Reference: "If the ext:q[] extension is present, insn:fcvt.q.h[] or insn:fcvt.h.q[] converts a half-precision fl..."
      Current:   "If the ext:q[] extension is present, insnlink:fcvt.q.h[] or insnlink:fcvt.h.q[] converts a half-prec..."
  * "norm:fcvt-q-w_fcvt-q-l_op":
      Reference: "insn:fcvt.q.w[] or insn:fcvt.q.l[] converts a 32-bit or 64-bit signed integer, respectively, into a ..."
      Current:   "insnlink:fcvt.q.w[] or insnlink:fcvt.q.l[] converts a 32-bit or 64-bit signed integer, respectively,..."
  * "norm:fcvt-s-d_fcvt-d-s_op":
      Reference: "The double-precision to single-precision and single-precision to
double-precision conversion instruc..."
      Current:   "The double-precision to single-precision and single-precision to
double-precision conversion instruc..."
  * "norm:fcvt-s-h_fcvt-h-s_op":
      Reference: "insn:fcvt.s.h[] or insn:fcvt.h.s[] converts a half-precision floating-point number to a single-preci..."
      Current:   "insnlink:fcvt.s.h[] or insnlink:fcvt.h.s[] converts a half-precision floating-point number to a sing..."
  * "norm:fcvt-s-q_fcvt-q-s_op":
      Reference: "insn:fcvt.s.q[] or
insn:fcvt.q.s[] converts a quad-precision floating-point number to a
single-preci..."
      Current:   "insnlink:fcvt.s.q[] or
insnlink:fcvt.q.s[] converts a quad-precision floating-point number to a
sing..."
  * "norm:fcvt-s-w_fcvt-s-l_op":
      Reference: "insn:fcvt.s.w[] or insn:fcvt.s.l[] converts a 32-bit or 64-bit signed
integer, respectively, in inte..."
      Current:   "insnlink:fcvt.s.w[] or insnlink:fcvt.s.l[] converts a 32-bit or 64-bit signed
integer, respectively,..."
  * "norm:fcvt-w-d_fcvt-l-d_op":
      Reference: "insn:fcvt.w.d[] or
insn:fcvt.l.d[] converts a double-precision floating-point number in
floating-poi..."
      Current:   "insnlink:fcvt.w.d[] or
insnlink:fcvt.l.d[] converts a double-precision floating-point number in
floa..."
  * "norm:fcvt-w-d_fcvt-wu-d_sign_ext":
      Reference: "For RV64, insn:fcvt.w.d[] and insn:fcvt.wu.d[] sign-extend the
32-bit result"
      Current:   "For RV64, insnlink:fcvt.w.d[] and insnlink:fcvt.wu.d[] sign-extend the
32-bit result"
  * "norm:fcvt-w-h_fcvt-l-h_op":
      Reference: "insn:fcvt.w.h[] or insn:fcvt.l.h[] converts a half-precision floating-point number to a signed 32-bi..."
      Current:   "insnlink:fcvt.w.h[] or insnlink:fcvt.l.h[] converts a half-precision floating-point number to a sign..."
  * "norm:fcvt-w-q_fcvt-l-q_op":
      Reference: "insn:fcvt.w.q[] or insn:fcvt.l.q[] converts a quad-precision floating-point number to a signed 32-bi..."
      Current:   "insnlink:fcvt.w.q[] or insnlink:fcvt.l.q[] converts a quad-precision floating-point number to a sign..."
  * "norm:fcvt-wu-d_fcvt-lu-d_fcvt-d-wu_fcvt-d-lu_op":
      Reference: "insn:fcvt.wu.d[], insn:fcvt.lu.d[], insn:fcvt.d.wu[], and insn:fcvt.d.lu[] variants convert to
or fr..."
      Current:   "insnlink:fcvt.wu.d[], insnlink:fcvt.lu.d[], insnlink:fcvt.d.wu[], and insnlink:fcvt.d.lu[] variants ..."
  * "norm:fcvt-wu-h_fcvt-lu-h_fcvt-h-wu_fcvt-h-lu_op":
      Reference: "insn:fcvt.wu.h[], insn:fcvt.lu.h[], insn:fcvt.h.wu[], and insn:fcvt.h.lu[] variants convert to or fr..."
      Current:   "insnlink:fcvt.wu.h[], insnlink:fcvt.lu.h[], insnlink:fcvt.h.wu[], and insnlink:fcvt.h.lu[] variants ..."
  * "norm:fcvt-wu-q_fcvt-lu-q_fcvt-q-wu_fcvt-q-lu_op":
      Reference: "insn:fcvt.wu.q[], insn:fcvt.lu.q[], insn:fcvt.q.wu[], and insn:fcvt.q.lu[] variants convert to or fr..."
      Current:   "insnlink:fcvt.wu.q[], insnlink:fcvt.lu.q[], insnlink:fcvt.q.wu[], and insnlink:fcvt.q.lu[] variants ..."
  * "norm:fcvt-wu-s_fcvt-lu-s_fcvt-s-wu_fcvt-s-lu_op":
      Reference: "insn:fcvt.wu.s[], insn:fcvt.lu.s[], insn:fcvt.s.wu[],
and insn:fcvt.s.lu[] variants convert to or fr..."
      Current:   "insnlink:fcvt.wu.s[], insnlink:fcvt.lu.s[], insnlink:fcvt.s.wu[],
and insnlink:fcvt.s.lu[] variants ..."
  * "norm:fcvt_float_rounding":
      Reference: "insn:fcvt.s.d[] rounds according to the rm field; insn:fcvt.d.s[] will
never round"
      Current:   "insnlink:fcvt.s.d[] rounds according to the rm field; insnlink:fcvt.d.s[] will
never round"
  * "norm:fcvt_int_double_valid_input":
      Reference: "The range of valid inputs for insn:fcvt.w.d[], insn:fcvt.wu.d[], insn:fcvt.l.d[], and insn:fcvt.lu.d..."
      Current:   "The range of valid inputs for insnlink:fcvt.w.d[], insnlink:fcvt.wu.d[], insnlink:fcvt.l.d[], and in..."
  * "norm:fcvt_int_float_valid_input":
      Reference: "<<int_conv>> gives the range of valid inputs
for insn:fcvt.w.s[], insn:fcvt.wu.s[], insn..."
      Current:   "<<int_conv>> gives the range of valid inputs
for insnlink:fcvt.w.s[], insnlink:fcvt.wu.s..."
  * "norm:fcvt_int_quad_valid_input":
      Reference: "The range of valid inputs for insn:fcvt.w.q[], insn:fcvt.wu.q[], insn:fcvt.l.q[], and insn:fcvt.lu.q..."
      Current:   "The range of valid inputs for insnlink:fcvt.w.q[], insnlink:fcvt.wu.q[], insnlink:fcvt.l.q[], and in..."
  * "norm:fcvt_long_double_rv64_only":
      Reference: "insn:fcvt.l.d[], fcvt.lu.d[], fcvt.d.l[], and fcvt.d.lu[] are RV64-only instructions."
      Current:   "insnlink:fcvt.l.d[], fcvt.lu.d[], fcvt.d.l[], and fcvt.d.lu[] are RV64-only instructions."
  * "norm:fcvt_long_float_rv64_only":
      Reference: "insn:fcvt.l.s[], insn:fcvt.lu.s[], insn:fcvt.s.l[], and insn:fcvt.s.lu[] are RV64-only instructions"
      Current:   "insnlink:fcvt.l.s[], insnlink:fcvt.lu.s[], insnlink:fcvt.s.l[], and insnlink:fcvt.s.lu[] are RV64-on..."
  * "norm:fcvt_long_half_rv64_only":
      Reference: "insn:fcvt.l.h[], insn:fcvt.lu.h[], insn:fcvt.h.l[], and insn:fcvt.h.lu[] are RV64-only instructions."
      Current:   "insnlink:fcvt.l.h[], insnlink:fcvt.lu.h[], insnlink:fcvt.h.l[], and insnlink:fcvt.h.lu[] are RV64-on..."
  * "norm:fcvt_long_quad_rv64_only":
      Reference: "insn:fcvt.l.q[], insn:fcvt.lu.q[], insn:fcvt.q.l[], and insn:fcvt.q.lu[] are RV64-only instructions"
      Current:   "insnlink:fcvt.l.q[], insnlink:fcvt.lu.q[], insnlink:fcvt.q.l[], and insnlink:fcvt.q.lu[] are RV64-on..."
  * "norm:fcvt_round":
      Reference: "All floating-point to integer and integer to floating-point conversion instructions round according ..."
      Current:   "All floating-point to integer and integer to floating-point conversion instructions round according ..."
  * "norm:fcvtmod-w-d_flags":
      Reference: "Floating-point exception flags are raised the same as they would be for insn:fcvt.w.d[] with the sam..."
      Current:   "Floating-point exception flags are raised the same as they would be for insnfcvt.w.d with the same i..."
  * "norm:fcvtmod-w-d_op":
      Reference: "The insn:fcvtmod.w.d[] instruction is defined similarly to the insn:fcvt.w.d[] instruction, with the..."
      Current:   "The insnfcvtmod.w.d instruction is defined similarly to the insnfcvt.w.d instruction, with the follo..."
  * "norm:fcvtmod-w-d_rsw":
      Reference: "It
is encoded like insn:fcvt.w.d[], but with the rs2 field set to 8 and the rm
field set to 1 (RTZ)...."
      Current:   "It
is encoded like insnlink:fcvt.w.d[], but with the rs2 field set to 8 and the rm
field set to 1 (R..."
  * "norm:fdiv-s_op":
      Reference: "insn:fdiv.s[] performs the single-precision floating-point division of rs1 by rs2"
      Current:   "insnlink:fdiv.s[] performs the single-precision floating-point division of rs1 by rs2"
  * "norm:fence-tso_op":
      Reference: "insn:fence.tso[] orders
all load operations in its predecessor set before all memory operations
in i..."
      Current:   "insnlink:fence.tso[] orders
all load operations in its predecessor set before all memory operations
..."
  * "norm:fence-tso_ordering_rw_rw_ok":
      Reference: "Because insn:fence[RW,RW] imposes a superset of the orderings that insn:fence.tso[] imposes, it is c..."
      Current:   "Because insnRW,RW imposes a superset of the orderings that insnfence.tso imposes, it is correct to i..."
  * "norm:fence_cons_ok":
      Reference: "We chose a relaxed memory model to allow high performance from simple machine implementations and fr..."
      Current:   "We chose a relaxed memory model to allow high performance from simple machine implementations and fr..."
  * "norm:fence_i_op":
      Reference: "A insn:fence.i[] instruction orders all explicit memory accesses that precede the insn:fence.i[] in ..."
      Current:   "A insnfence.i instruction orders all explicit memory accesses that precede the insnfence.i in progra..."
  * "norm:fence_i_rsv":
      Reference: "The unused fields in the insn:fence.i[] instruction, funct12, rs1, and rd, are reserved for finer-gr..."
      Current:   "The unused fields in the insnfence.i instruction, funct12, rs1, and rd, are reserved for finer-grain..."
  * "norm:fence_op":
      Reference: "A insn:fence[] (with fm=0000) orders all memory operations in its predecessor set
before all memory ..."
      Current:   "A insnlink:fence[] (with fm=0000) orders all memory operations in its predecessor set
before all mem..."
  * "norm:fence_unused_flds_rsv":
      Reference: "The unused fields in the
insn:fence[] instructions, rs1 and rd, are reserved
for finer-grain fences ..."
      Current:   "The unused fields in the
insnlink:fence[] instructions, rs1 and rd, are reserved
for finer-grain fen..."
  * "norm:feq-s_flt-s_fle-s_op":
      Reference: "Floating-point compare instructions (insn:feq.s[], insn:flt.s[], insn:fle.s[]) perform the specified..."
      Current:   "Floating-point compare instructions (insnfeq.s, insnflt.s, insnfle.s) perform the specified comparis..."
  * "norm:feq-s_quiet":
      Reference: "insn:feq.s[] performs a quiet comparison: it only sets
the invalid operation exception flag if eithe..."
      Current:   "insnlink:feq.s[] performs a quiet comparison: it only sets
the invalid operation exception flag if e..."
  * "norm:fld_fsd_atomic_align":
      Reference: "insn:fld[] and insn:fsd[] are only guaranteed to execute atomically if the effective address is natu..."
      Current:   "insnfld and insnfsd are only guaranteed to execute atomically if the effective address is naturally ..."
  * "norm:fld_fsd_bits_maintained":
      Reference: "insn:fld[] and insn:fsd[] do not modify the bits being transferred; in particular, the payloads of n..."
      Current:   "insnfld and insnfsd do not modify the bits being transferred; in particular, the payloads of non-can..."
  * "norm:fld_op":
      Reference: "The insn:fld[] instruction loads a double-precision floating-point value from
memory into floating-p..."
      Current:   "The insnlink:fld[] instruction loads a double-precision floating-point value from
memory into floati..."
  * "norm:fleq-d_fltq-d_op":
      Reference: "If the ext:d[] extension is implemented, insn:fleq.d[] and insn:fltq.d[] instructions are analogousl..."
      Current:   "If the ext:d[] extension is implemented, insnfleq.d and insnfltq.d instructions are analogously defi..."
  * "norm:fleq-h_fltq-h_op":
      Reference: "If the ext:zfh[] extension is implemented, insn:fleq.h[] and insn:fltq.h[] instructions are analogou..."
      Current:   "If the ext:zfh[] extension is implemented, insnfleq.h and insnfltq.h instructions are analogously de..."
  * "norm:fleq-q_fltq-q_op":
      Reference: "If the ext:q[] extension is implemented, insn:fleq.q[] and insn:fltq.q[] instructions are analogousl..."
      Current:   "If the ext:q[] extension is implemented, insnfleq.q and insnfltq.q instructions are analogously defi..."
  * "norm:fleq-s_fltq-s_op":
      Reference: "The insn:fleq.s[] and insn:fltq.s[] instructions are defined like the insn:fle.s[] and insn:flt.s[] ..."
      Current:   "The insnfleq.s and insnfltq.s instructions are defined like the insnfle.s and insnflt.s instructions..."
  * "norm:fli-d_op":
      Reference: "If the ext:d[] extension is implemented, insn:fli.d[] performs the analogous operation, but loads a ..."
      Current:   "If the ext:d[] extension is implemented, insnfli.d performs the analogous operation, but loads a dou..."
  * "norm:fli-h_op":
      Reference: "If the ext:zfh[] or ext:zvfh[] extension is implemented, insn:fli.h[] performs the analogous operati..."
      Current:   "If the ext:zfh[] or ext:zvfh[] extension is implemented, insnfli.h performs the analogous operation,..."
  * "norm:fli-q_op":
      Reference: "If the ext:q[] extension is implemented, insn:fli.q[] performs the analogous operation, but loads a ..."
      Current:   "If the ext:q[] extension is implemented, insnfli.q performs the analogous operation, but loads a qua..."
  * "norm:fli-s_op":
      Reference: "The insn:fli.s[] instruction loads one of 32 single-precision floating-point constants, encoded in t..."
      Current:   "The insnfli.s instruction loads one of 32 single-precision floating-point constants, encoded in the ..."
  * "norm:flt-s_fle-s_signaling":
      Reference: "insn:flt.s[] and insn:fle.s[] perform what IEEE 754-2008
refers to as signaling comparisons: that is..."
      Current:   "insnlink:flt.s[] and insnlink:fle.s[] perform what IEEE 754-2008
refers to as signaling comparisons:..."
  * "norm:fmadd-s_op":
      Reference: "insn:fmadd.s[] multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final res..."
      Current:   "insnfmadd.s multiplies the values in rs1 and rs2, adds the value in rs3, and writes the final result..."
  * "norm:fmaxm-d_fminm-d_op":
      Reference: "If the ext:d[] extension is implemented, insn:fminm.d[] and insn:fmaxm.d[] instructions are analogou..."
      Current:   "If the ext:d[] extension is implemented, insnfminm.d and insnfmaxm.d instructions are analogously de..."
  * "norm:fmaxm-h_fminm-h_op":
      Reference: "If the ext:zfh[] extension is implemented, insn:fminm.h[] and insn:fmaxm.h[] instructions are analog..."
      Current:   "If the ext:zfh[] extension is implemented, insnfminm.h and insnfmaxm.h instructions are analogously ..."
  * "norm:fmaxm-q_fminm-q_op":
      Reference: "If the ext:q[] extension is implemented, insn:fminm.q[] and insn:fmaxm.q[] instructions are analogou..."
      Current:   "If the ext:q[] extension is implemented, insnfminm.q and insnfmaxm.q instructions are analogously de..."
  * "norm:fmaxm-s_fminm-s_op":
      Reference: "The insn:fminm.s[] and insn:fmaxm.s[] instructions are defined like the insn:fmin.s[] and insn:fmax...."
      Current:   "The insnfminm.s and insnfmaxm.s instructions are defined like the insnfmin.s and insnfmax.s instruct..."
  * "norm:fmin-s_fmax-s_op":
      Reference: "Floating-point minimum-number and maximum-number instructions insn:fmin.s[] and insn:fmax.s[] write,..."
      Current:   "Floating-point minimum-number and maximum-number instructions insnlink:fmin.s[] and insnlink:fmax.s[..."
  * "norm:fmsub-s_op":
      Reference: "insn:fmsub.s[] multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the fina..."
      Current:   "insnfmsub.s multiplies the values in rs1 and rs2, subtracts the value in rs3, and writes the final r..."
  * "norm:fmv-d-x_op":
      Reference: "insn:fmv.d.x[] moves the
double-precision value encoded in the IEEE 754-2008 encoding from the
integ..."
      Current:   "insnlink:fmv.d.x[] moves the
double-precision value encoded in the IEEE 754-2008 encoding from the
i..."
  * "norm:fmv-h-x_op":
      Reference: "insn:fmv.h.x[] moves the half-precision value encoded in the IEEE 754-2008 encoding from the lower 1..."
      Current:   "insnfmv.h.x moves the half-precision value encoded in the IEEE 754-2008 encoding from the lower 16 b..."
  * "norm:fmv-w-x_op":
      Reference: "insn:fmv.w.x[] moves the single-precision value encoded in the IEEE 754-2008 encoding from the lower..."
      Current:   "insnfmv.w.x moves the single-precision value encoded in the IEEE 754-2008 encoding from the lower 32..."
  * "norm:fmv-x-d_op":
      Reference: "insn:fmv.x.d[] moves the double-precision value in
floating-point register rs1 to a representation i..."
      Current:   "insnlink:fmv.x.d[] moves the double-precision value in
floating-point register rs1 to a representati..."
  * "norm:fmv-x-h_op":
      Reference: "insn:fmv.x.h[] moves
the half-precision value in floating-point register rs1 to a
representation in ..."
      Current:   "insnlink:fmv.x.h[] moves
the half-precision value in floating-point register rs1 to a
representation..."
  * "norm:fmv-x-w_op":
      Reference: "insn:fmv.x.w[] moves
the single-precision value in floating-point register rs1 represented
in the IE..."
      Current:   "insnlink:fmv.x.w[] moves
the single-precision value in floating-point register rs1 represented
in th..."
  * "norm:fmv_bits_preserved":
      Reference: "insn:fmv.x.d[] and insn:fmv.d.x[] do not modify the bits being transferred; in particular, the paylo..."
      Current:   "insnfmv.x.d and insnfmv.d.x do not modify the bits being transferred; in particular, the payloads of..."
  * "norm:fmv_half_bits_preserved":
      Reference: "insn:fmv.x.h[] and insn:fmv.h.x[] do not modify the bits being transferred; in particular, the paylo..."
      Current:   "insnfmv.x.h and insnfmv.h.x do not modify the bits being transferred; in particular, the payloads of..."
  * "norm:fmvh-x-d_op":
      Reference: "For RV32 only, if the ext:d[] extension is implemented, the insn:fmvh.x.d[] instruction moves bits 6..."
      Current:   "For RV32 only, if the ext:d[] extension is implemented, the insnfmvh.x.d instruction moves bits 63:3..."
  * "norm:fmvh-x-q_op":
      Reference: "For RV64 only, if the ext:q[] extension is implemented, the insn:fmvh.x.q[] instruction moves bits 1..."
      Current:   "For RV64 only, if the ext:q[] extension is implemented, the insnfmvh.x.q instruction moves bits 127:..."
  * "norm:fmvp-d-x_op":
      Reference: "For RV32 only, if the ext:d[] extension is implemented, the insn:fmvp.d.x[] instruction moves a doub..."
      Current:   "For RV32 only, if the ext:d[] extension is implemented, the insnfmvp.d.x instruction moves a double-..."
  * "norm:fmvp-q-x_op":
      Reference: "For RV64 only, if the ext:q[] extension is implemented, the insn:fmvp.q.x[] instruction moves a doub..."
      Current:   "For RV64 only, if the ext:q[] extension is implemented, the insnfmvp.q.x instruction moves a double-..."
  * "norm:fnmadd-s_op":
      Reference: "insn:fnmadd.s[] multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs..."
      Current:   "insnfnmadd.s multiplies the values in rs1 and rs2, negates the product, subtracts the value in rs3, ..."
  * "norm:fnmsub-s_op":
      Reference: "insn:fnmsub.s[] multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, an..."
      Current:   "insnfnmsub.s multiplies the values in rs1 and rs2, negates the product, adds the value in rs3, and w..."
  * "norm:fround-d_froundnx-d_op":
      Reference: "If the ext:d[] extension is implemented, insn:fround.d[] and insn:froundnx.d[] instructions are anal..."
      Current:   "If the ext:d[] extension is implemented, insnfround.d and insnfroundnx.d instructions are analogousl..."
  * "norm:fround-h_froundnx-h_op":
      Reference: "If the ext:zfh[] extension is implemented, insn:fround.h[] and insn:froundnx.h[] instructions are an..."
      Current:   "If the ext:zfh[] extension is implemented, insnfround.h and insnfroundnx.h instructions are analogou..."
  * "norm:fround-q_froundnx-q_op":
      Reference: "If the ext:q[] extension is implemented, insn:fround.q[] and insn:froundnx.q[] instructions are anal..."
      Current:   "If the ext:q[] extension is implemented, insnfround.q and insnfroundnx.q instructions are analogousl..."
  * "norm:fround-s_op":
      Reference: "The insn:fround.s[] instruction rounds the single-precision floating-point
number in floating-point ..."
      Current:   "The insnlink:fround.s[] instruction rounds the single-precision floating-point
number in floating-po..."
  * "norm:froundnx-s_op":
      Reference: "The insn:froundnx.s[] instruction is defined similarly, but it also sets the inexact exception flag ..."
      Current:   "The insnfroundnx.s instruction is defined similarly, but it also sets the inexact exception flag if ..."
  * "norm:fsd_op":
      Reference: "insn:fsd[] stores a double-precision
value from the floating-point registers to memory"
      Current:   "insnlink:fsd[] stores a double-precision
value from the floating-point registers to memory"
  * "norm:fsgnj-d_fsgnjn-d_fsgnjx-d_op":
      Reference: "Floating-point to floating-point sign-injection instructions, insn:fsgnj.d[], insn:fsgnjn.d[], and i..."
      Current:   "Floating-point to floating-point sign-injection instructions, insnfsgnj.d, insnfsgnjn.d, and insnfsg..."
  * "norm:fsgnj-h_fsgnjn-h_fsgnjx-h_op":
      Reference: "Floating-point to floating-point sign-injection instructions, insn:fsgnj.h[], insn:fsgnjn.h[], and i..."
      Current:   "Floating-point to floating-point sign-injection instructions, insnfsgnj.h, insnfsgnjn.h, and insnfsg..."
  * "norm:fsgnj-q_fsgnjn-q_fsgnjx-q_op":
      Reference: "Floating-point to floating-point sign-injection instructions, insn:fsgnj.q[], insn:fsgnjn.q[], and i..."
      Current:   "Floating-point to floating-point sign-injection instructions, insnfsgnj.q, insnfsgnjn.q, and insnfsg..."
  * "norm:fsgnj-s_fsgnjn-s_fsgnjx-s_op":
      Reference: "insn:fsgnj.s[], insn:fsgnjn.s[], and
insn:fsgnjx.s[] are floating-point to floating-point sign-injec..."
      Current:   "insnlink:fsgnj.s[], insnlink:fsgnjn.s[], and
insnlink:fsgnjx.s[] are floating-point to floating-poin..."
  * "norm:fsh_flh_atomic_align":
      Reference: "insn:flh[] and insn:fsh[] are only guaranteed to execute atomically if the effective address is natu..."
      Current:   "insnflh and insnfsh are only guaranteed to execute atomically if the effective address is naturally ..."
  * "norm:fsh_flh_bits_maintained":
      Reference: "insn:flh[] and insn:fsh[] do not modify the bits being transferred; in particular, the payloads of n..."
      Current:   "insnflh and insnfsh do not modify the bits being transferred; in particular, the payloads of non-can..."
  * "norm:fsq_flq_atomic_align":
      Reference: "insn:flq[] and insn:fsq[] are only guaranteed to execute atomically if the effective address is natu..."
      Current:   "insnflq and insnfsq are only guaranteed to execute atomically if the effective address is naturally ..."
  * "norm:fsq_flq_bits_maintained":
      Reference: "insn:flq[] and insn:fsq[] do not modify the bits being transferred; in particular, the payloads of n..."
      Current:   "insnflq and insnfsq do not modify the bits being transferred; in particular, the payloads of non-can..."
  * "norm:fsqrt-s_op":
      Reference: "insn:fsqrt.s[] computes the square root of rs1"
      Current:   "insnlink:fsqrt.s[] computes the square root of rs1"
  * "norm:fsub-s_op":
      Reference: "insn:fsub.s[] performs the single-precision floating-point subtraction of rs2 from rs1"
      Current:   "insnlink:fsub.s[] performs the single-precision floating-point subtraction of rs2 from rs1"
  * "norm:fsw_flw_atomic_align":
      Reference: "insn:flw[] and insn:fsw[] are only guaranteed to execute atomically if the effective address is natu..."
      Current:   "insnflw and insnfsw are only guaranteed to execute atomically if the effective address is naturally ..."
  * "norm:fsw_flw_bits_maintained":
      Reference: "insn:flw[] and insn:fsw[] do not modify the bits being transferred; in particular, the payloads of n..."
      Current:   "insnflw and insnfsw do not modify the bits being transferred; in particular, the payloads of non-can..."
  * "norm:fsw_flw_op":
      Reference: "Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, w..."
      Current:   "Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, w..."
  * "norm:hfence-gvma_op":
      Reference: "insn:hfence.gvma[] is valid only in HS-mode when csr:mstatus[tvm]=0, or in M-mode (irrespective of c..."
      Current:   "insnhfence.gvma is valid only in HS-mode when csr:mstatus[tvm]=0, or in M-mode (irrespective of csr:..."
  * "norm:hints_enc":
      Reference: "Most RV32I HINTs are encoded as integer computational instructions with
rd=x0. The other RV32I HINTs..."
      Current:   "Most RV32I HINTs are encoded as integer computational instructions with
rd=x0. The other RV32I HINTs..."
  * "norm:jal_op":
      Reference: "insn:jal[] stores the address of the instruction
following the jump (pc+4) into register rd."
      Current:   "insnlink:jal[] stores the address of the instruction
following the jump (pc+4) into register rd."
  * "norm:jump_misaligned_exception":
      Reference: "The insn:jal[] and insn:jalr[] instructions will generate an instruction-address-misaligned exceptio..."
      Current:   "The insnjal and insnjalr instructions will generate an instruction-address-misaligned exception if t..."
  * "norm:lb_lbu_op":
      Reference: "insn:lb[] and insn:lbu[] are defined analogously for 8-bit values."
      Current:   "insnlink:lb[] and insnlink:lbu[] are defined analogously for 8-bit values."
  * "norm:ld_op_rv64i":
      Reference: "The insn:ld[] instruction loads a 64-bit value from memory into register rd
for RV64I."
      Current:   "The insnlink:ld[] instruction loads a 64-bit value from memory into register rd
for RV64I."
  * "norm:lh_lhu_lb_lbu_op_rv64i":
      Reference: "insn:lh[] and insn:lhu[] are defined analogously for 16-bit values,
as are insn:lb[] and insn:lbu[] ..."
      Current:   "insnlink:lh[] and insnlink:lhu[] are defined analogously for 16-bit values,
as are insnlink:lb[] and..."
  * "norm:lh_op":
      Reference: "insn:lh[] loads a 16-bit value from memory, then sign-extends to 32-bits before storing
in rd."
      Current:   "insnlink:lh[] loads a 16-bit value from memory, then sign-extends to 32-bits before storing
in rd."
  * "norm:lhu_op":
      Reference: "insn:lhu[] loads a 16-bit value from memory but then zero extends to
32-bits before storing in rd."
      Current:   "insnlink:lhu[] loads a 16-bit value from memory but then zero extends to
32-bits before storing in r..."
  * "norm:lpad_sw_exception":
      Reference: "The software-check exception due to the instruction not being an insn:lpad[] instruction when ELP is..."
      Current:   "The software-check exception due to the instruction not being an insnlpad instruction when ELP is LP..."
  * "norm:lr_sc_rv64":
      Reference: "insn:lr.d[] and
insn:sc.d[] act analogously on doublewords and are only available on RV64. For
RV64,..."
      Current:   "insnlink:lr.d[] and
insnlink:sc.d[] act analogously on doublewords and are only available on RV64. F..."
  * "norm:lr_w_op":
      Reference: "insn:lr.w[] loads a word from the address in rs1, places the
sign-extended value in rd, and register..."
      Current:   "insnlink:lr.w[] loads a word from the address in rs1, places the
sign-extended value in rd, and regi..."
  * "norm:lui_op":
      Reference: "insn:lui[] places the 32-bit U-immediate value into the
destination register rd, filling in the lowe..."
      Current:   "insnlink:lui[] places the 32-bit U-immediate value into the
destination register rd, filling in the ..."
  * "norm:lui_op_rv64i":
      Reference: "insn:lui[] places the
32-bit U-immediate into register rd, filling in the lowest 12 bits
with zeros...."
      Current:   "insnlink:lui[] places the
32-bit U-immediate into register rd, filling in the lowest 12 bits
with ze..."
  * "norm:lw_op":
      Reference: "The insn:lw[] instruction loads a 32-bit value from memory into rd."
      Current:   "The insnlink:lw[] instruction loads a 32-bit value from memory into rd."
  * "norm:lw_op_rv64i":
      Reference: "The insn:lw[] instruction loads a 32-bit value from memory and sign-extends
this to 64 bits before s..."
      Current:   "The insnlink:lw[] instruction loads a 32-bit value from memory and sign-extends
this to 64 bits befo..."
  * "norm:lwu_op":
      Reference: "The insn:lwu[] instruction, on the other hand, zero-extends the 32-bit value from
memory for RV64I."
      Current:   "The insnlink:lwu[] instruction, on the other hand, zero-extends the 32-bit value from
memory for RV6..."
  * "norm:marchid_sz_acc_op":
      Reference: "The marchid CSR is an MXLEN-bit read-only register encoding the base
microarchitecture of the hart."
      Current:   "The csr:marchid[] CSR is an MXLEN-bit read-only register encoding the base
microarchitecture of the ..."
  * "norm:mhartid_sz_acc_op":
      Reference: "The mhartid CSR is an MXLEN-bit read-only register containing the
integer ID of the hardware thread ..."
      Current:   "The csr:mhartid[] CSR is an MXLEN-bit read-only register containing the
integer ID of the hardware t..."
  * "norm:mimpid_op":
      Reference: "The mimpid CSR provides a unique encoding of the version of the
processor implementation."
      Current:   "The csr:mimpid[] CSR provides a unique encoding of the version of the
processor implementation."
  * "norm:misa_acc":
      Reference: "The misa CSR is a WARL read-write register"
      Current:   "The csr:misa[] CSR is a WARL read-write register"
  * "norm:misa_extensions_disabling":
      Reference: "When a standard extension is disabled by clearing its bit in misa, the instructions and CSRs defined..."
      Current:   "When a standard extension is disabled by clearing its bit in csr:misa[], the instructions and CSRs d..."
  * "norm:misa_extensions_disabling_def":
      Reference: "With this definition of implemented, disabling an extension by clearing its bit in misa results in t..."
      Current:   "With this definition of implemented, disabling an extension by clearing its bit in csr:misa[] result..."
  * "norm:misa_extensions_enc_tbl":
      Reference: "Bit|Character|Description
===
0|A|Atomic extension¶1|B|B extension¶2|C|Compressed extension¶3|D|Doub..."
      Current:   "Bit|Character|Description
===
0|csr::[a]|Atomic extension¶1|csr::[b]|B extension¶2|csr::[c]|Compress..."
  * "norm:misa_extensions_impl_def":
      Reference: "For a given RISC-V execution environment, an instruction, extension, or other feature of the RISC-V ..."
      Current:   "For a given RISC-V execution environment, an instruction, extension, or other feature of the RISC-V ..."
  * "norm:misa_inc_ialign":
      Reference: "Writing misa may increase IALIGN, e.g., by disabling the
ext:c[] extension. If an instruction that w..."
      Current:   "Writing csr:misa[] may increase IALIGN, e.g., by disabling the
ext:c[] extension. If an instruction ..."
  * "norm:misa_mxl_acc":
      Reference: "The MXL field is read-only."
      Current:   "The csr::[mxl] field is read-only."
  * "norm:misa_mxl_enc":
      Reference: "MXL|XLEN
===
1
2
3|32
64
Reserved
==="
      Current:   "MXL|XLEN
===
1|32¶2|64¶3|Reserved
==="
  * "norm:misa_mxl_op_isa":
      Reference: "The MXL (Machine XLEN) field encodes the native base integer ISA width as
shown in <<norm:misa..."
      Current:   "The csr::[mxl] (Machine XLEN) field encodes the native base integer ISA width as
shown in <<no..."
  * "norm:misa_mxl_op_nz":
      Reference: "If misa is nonzero, the
MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN."
      Current:   "If csr:misa[] is nonzero, the
csr::[mxl] field indicates the effective XLEN in M-mode, a constant te..."
  * "norm:misa_sz":
      Reference: "The misa CSR is MXLEN bits wide."
      Current:   "The csr:misa[] CSR is MXLEN bits wide."
  * "norm:mstatus_fs_acc1":
      Reference: "If the F extension is implemented, the FS field shall not be read-only zero."
      Current:   "If the ext:f[] extension is implemented, the csr::[fs] field shall not be read-only zero."
  * "norm:mstatus_fs_acc2":
      Reference: "If neither the F extension nor S-mode is implemented, then FS is read-only zero."
      Current:   "If neither the ext:f[] extension nor S-mode is implemented, then csr::[fs] is read-only zero."
  * "norm:mstatus_fs_no_change_dirty":
      Reference: "If an instruction explicitly or implicitly writes a floating-point
register or the fcsr but does not..."
      Current:   "If an instruction explicitly or implicitly writes a floating-point
register or the csr:fcsr[] but do..."
  * "norm:mstatus_fs_no_dirty_track":
      Reference: "dirtiness might not be tracked at all, in which case the valid FS states
are Off and Dirty, and an a..."
      Current:   "dirtiness might not be tracked at all, in which case the valid FS states
are Off and Dirty, and an a..."
  * "norm:mstatus_fs_op":
      Reference: "The FS field encodes the status of the
floating-point unit state, including the floating-point regis..."
      Current:   "The csr::[fs] field encodes the status of the
floating-point unit state, including the floating-poin..."
  * "norm:mstatus_fs_rdonly0_s_no_f":
      Reference: "If S-mode is implemented but the F extension is not, FS
may optionally be read-only zero."
      Current:   "If S-mode is implemented but the ext:f[] extension is not,
csr::[fs] may optionally be read-only zer..."
  * "norm:mstatus_fs_vs_warl":
      Reference: "The FS[1:0] and VS[1:0] WARL fields"
      Current:   "The csr::[fs][1:0] and csr::[vs][1:0] WARL fields"
  * "norm:mstatus_fs_vs_xs_enc":
      Reference: "Status|FS and VS Meaning|XS Meaning
===
0
1
2
3|Off
Initial
Clean
Dirty|All off
None dirty or clean,..."
      Current:   "Status|FS and VS Meaning|XS Meaning
===
0|Off|All off¶1|Initial|None dirty or clean, some on¶2|Clean..."
  * "norm:mstatus_fs_vs_xs_update_indep_priv":
      Reference: "The status fields will
also be updated during execution of instructions, regardless of privilege mod..."
      Current:   "The status fields are
also updated during execution of instructions, regardless of privilege mode."
  * "norm:mstatus_fs_wr":
      Reference: "Changing the setting of FS has no effect on the contents of the
floating-point register state. In pa..."
      Current:   "Changing the setting of csr::[fs] has no effect on the contents of the
floating-point register state..."
  * "norm:mstatus_mbe_op":
      Reference: "MBE controls whether non-instruction-fetch memory accesses made from M-mode (assuming mstatus.MPRV=0..."
      Current:   "csr::[mbe] controls whether non-instruction-fetch memory accesses made from M-mode (assuming csr:mst..."
  * "norm:mstatus_mdt_clr_mnret":
      Reference: "When the Smdbltrp extension is implemented, the MNRET instruction, provided by the Smrnmi extension,..."
      Current:   "When the ext:smdbltrp[] extension is implemented, the insnlink:mnret[] instruction, provided by the ..."
  * "norm:mstatus_mdt_clr_mret_sret":
      Reference: "The MDT bit is set to 0."
      Current:   "The csr::[mdt] bit is set to 0."
  * "norm:mstatus_mdt_not_set_rnmi":
      Reference: "A trap caused by an RNMI does not set the MDT bit."
      Current:   "A trap caused by an RNMI does not set the csr::[mdt] bit."
  * "norm:mstatus_mdt_rst":
      Reference: "Upon reset, the MDT field is set to 1."
      Current:   "Upon reset, the csr::[mdt] field is set to 1."
  * "norm:mstatus_mdt_sz_warl":
      Reference: "The M-mode-disable-trap (MDT) bit is a WARL field introduced by the Smdbltrp extension."
      Current:   "The M-mode-disable-trap (csr::[mdt]) bit is a WARL field introduced by the ext:smdbltrp[] extension."
  * "norm:mstatus_mie_clr_by_mdt":
      Reference: "When the MDT bit is set to 1 by an explicit CSR write,
the MIE (Machine Interrupt Enable) bit is cle..."
      Current:   "When the csr::[mdt] bit is set to 1 by an explicit CSR write,
the csr::[mie] (Machine Interrupt Enab..."
  * "norm:mstatus_mie_clr_by_mdt_rv64":
      Reference: "For RV64, this clearing occurs regardless of the value written, if any, to the MIE bit by the same w..."
      Current:   "For RV64, this clearing occurs regardless of the value written, if any, to the csr::[mie] bit by the..."
  * "norm:mstatus_mie_set_mdt_0":
      Reference: "The MIE bit can only be set to 1 by an
explicit CSR write if the MDT bit is already 0"
      Current:   "The csr::[mie] bit can only be set to 1 by an
explicit CSR write if the csr::[mdt] bit is already 0"
  * "norm:mstatus_mie_sie_op1":
      Reference: "Global interrupt-enable bits, MIE and SIE, are provided for M-mode and
S-mode respectively."
      Current:   "Global interrupt-enable bits, csr::[mie] and csr::[sie], are provided for M-mode and
S-mode respecti..."
  * "norm:mstatus_mpp_sz":
      Reference: "MPP is two bits wide"
      Current:   "csr::[mpp] is two bits wide"
  * "norm:mstatus_mprv_clr_mret_sret_less_priv":
      Reference: "An MRET or SRET instruction that changes the privilege mode to a mode
less privileged than M also se..."
      Current:   "An insnlink:mret[] or insnlink:sret[] instruction that changes the privilege mode to a mode
less pri..."
  * "norm:mstatus_mprv_inst_xlat_op":
      Reference: "Instruction address-translation and protection are unaffected by the
setting of MPRV."
      Current:   "Instruction address-translation and protection are unaffected by the
setting of csr::[mprv]."
  * "norm:mstatus_mprv_ldst_op":
      Reference: "When MPRV=0, explicit memory accesses
behave as normal, using the translation and
protection mechani..."
      Current:   "When csr::[mprv]=0, explicit memory accesses
behave as normal, using the translation and
protection ..."
  * "norm:mstatus_mprv_rdonly0_no_umode":
      Reference: "MPRV is read-only 0 if U-mode is not supported; otherwise, it must be writable."
      Current:   "csr::[mprv] is read-only 0 if U-mode is not supported; otherwise, it must be writable."
  * "norm:mstatus_mstatush_xbe_warl":
      Reference: "The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields that
control the endianness of me..."
      Current:   "The csr::[mbe], csr::[sbe], and csr::[ube] bits in csr:mstatus[] and csr:mstatush[] are WARL fields ..."
  * "norm:mstatus_mxr_op":
      Reference: "When MXR=0, only loads from pages marked readable (R=1 in <<sv32pte>>) will succeed.
Whe..."
      Current:   "When csr::[mxr]=0, only loads from pages marked readable (R=1 in <<sv32pte>>) will succe..."
  * "norm:mstatus_mxr_rdonly0_no_smode":
      Reference: "MXR is read-only 0 if S-mode is not supported or if satp.MODE is read-only 0; otherwise, it must be ..."
      Current:   "csr::[mxr] is read-only 0 if S-mode is not supported or if csr:satp[mode] is read-only 0; otherwise,..."
  * "norm:mstatus_mxr_sum_op_acc_fault":
      Reference: "The MXR and SUM mechanisms only affect the interpretation of permissions encoded in page-table entri..."
      Current:   "The csr::[mxr] and csr::[sum] mechanisms only affect the interpretation of permissions encoded in pa..."
  * "norm:mstatus_sbe_change_fence":
      Reference: "Since changing SBE alters the implementation’s interpretation of these
data structures, if any such ..."
      Current:   "Since changing csr::[sbe] alters the implementation’s interpretation of these
data structures, if an..."
  * "norm:mstatus_sbe_implicit":
      Reference: "For implicit accesses to supervisor-level memory management data
structures, such as page tables, en..."
      Current:   "For implicit accesses to supervisor-level memory management data
structures, such as page tables, en..."
  * "norm:mstatus_sbe_op":
      Reference: "If S-mode is not supported, SBE is read-only 0. Otherwise, SBE controls whether explicit load and st..."
      Current:   "If S-mode is not supported, csr::[sbe] is read-only 0. Otherwise, csr::[sbe] controls whether explic..."
  * "norm:mstatus_sbe_rocopy":
      Reference: "If S-mode is supported, an implementation may make SBE be a read-only
copy of MBE."
      Current:   "If S-mode is supported, an implementation may make csr::[sbe] be a read-only
copy of csr::[mbe]."
  * "norm:mstatus_sd_acc":
      Reference: "The SD bit is a read-only bit"
      Current:   "The csr::[sd] bit is a read-only bit"
  * "norm:mstatus_sd_op1":
      Reference: "summarizes whether either the FS, VS,
or XS fields signal the presence of some dirty state that will..."
      Current:   "summarizes whether either the csr::[fs], csr::[vs],
or csr::[xs] fields signal the presence of some ..."
  * "norm:mstatus_sd_rdonly0":
      Reference: "If FS, XS, and VS are all read-only zero, then SD is also always zero."
      Current:   "If csr::[fs], csr::[vs], and csr::[xs] are all read-only zero, then csr::[sd] is also always zero."
  * "norm:mstatus_sie_spie_rdonly0":
      Reference: "MIE and MPIE must be writable.
If supervisor mode is not implemented, then SIE and SPIE are read-onl..."
      Current:   "csr::[mie] and csr::[mpie] must be writable.
If supervisor mode is not implemented, then csr::[sie] ..."
  * "norm:mstatus_spp_sz":
      Reference: "SPP is one bit wide."
      Current:   "csr::[spp] is one bit wide."
  * "norm:mstatus_sum_op":
      Reference: "When SUM=0, S-mode memory accesses to pages that are accessible by U-mode
(U=1 in <<sv32pte&gt..."
      Current:   "When csr::[sum]=0, S-mode memory accesses to pages that are accessible by U-mode
(U=1 in <<sv3..."
  * "norm:mstatus_sum_op_mprv_mpp":
      Reference: "while SUM is ordinarily ignored when not
executing in S-mode, it is in effect when MPRV=1 and MPP=S."
      Current:   "while csr::[sum] is ordinarily ignored when not
executing in S-mode, it is in effect when csr::[mprv..."
  * "norm:mstatus_sum_op_no-vm":
      Reference: "SUM has no effect when page-based virtual memory is not in effect."
      Current:   "csr::[sum] has no effect when page-based virtual memory is not in effect."
  * "norm:mstatus_sum_rdonly0":
      Reference: "SUM is read-only 0 if S-mode is not supported or if satp.MODE is read-only 0; otherwise, it must be ..."
      Current:   "csr::[sum] is read-only 0 if S-mode is not supported or if csr:satp[mode] is read-only 0; otherwise,..."
  * "norm:mstatus_sxl_acc_mxlen64":
      Reference: "When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.
Otherwise, it is a WARL field..."
      Current:   "When MXLEN=64, if S-mode is not supported, then csr::[sxl] is read-only zero.
Otherwise, it is a WAR..."
  * "norm:mstatus_sxl_rdonly_mxlen64":
      Reference: "an implementation may make SXL be a read-only field whose
value always ensures that SXLEN=MXLEN."
      Current:   "an implementation may make csr::[sxl] be a read-only field whose
value always ensures that SXLEN=MXL..."
  * "norm:mstatus_sxl_uxl_enc":
      Reference: "The encoding of these fields is the same as the MXL field of misa, shown in <<norm:misa_mxl_en..."
      Current:   "The encoding of these fields is the same as the csr::[mxl] field of csr:misa[], shown in <<nor..."
  * "norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32":
      Reference: "When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32."
      Current:   "When MXLEN=32, the csr::[sxl] and csr::[uxl] fields do not exist, and SXLEN=32 and UXLEN=32."
  * "norm:mstatus_sxl_uxl_warl_op":
      Reference: "For RV64 harts, the SXL and UXL fields are WARL fields that control the
value of XLEN for S-mode and..."
      Current:   "For RV64 harts, the csr::[sxl] and csr::[uxl] fields are WARL fields that control the
value of XLEN ..."
  * "norm:mstatus_sz_acc":
      Reference: "The mstatus register is an MXLEN-bit read/write register formatted as
shown in <<mstatusreg-rv..."
      Current:   "The csr:mstatus[] register is an MXLEN-bit read/write register formatted as
shown in <<mstatus..."
  * "norm:mstatus_tsr_acc":
      Reference: "TSR is read-only 0 when S-mode is not supported;
otherwise, it must be writable."
      Current:   "csr::[tsr] is read-only 0 when S-mode is not supported;
otherwise, it must be writable."
  * "norm:mstatus_tsr_op":
      Reference: "When TSR=1, attempts to
execute SRET while executing in S-mode will raise an illegal-instruction
exc..."
      Current:   "When csr::[tsr]=1, attempts to
execute insn:sret[] while executing in S-mode will raise an illegal-i..."
  * "norm:mstatus_tsr_warl":
      Reference: "The TSR (Trap SRET) bit is a WARL field that supports intercepting the
supervisor exception return i..."
      Current:   "The csr::[tsr] (Trap insn:sret[]) bit is a WARL field that supports intercepting the
supervisor exce..."
  * "norm:mstatus_tvm_warl_op":
      Reference: "The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memo..."
      Current:   "The csr::[tvm] (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtu..."
  * "norm:mstatus_tw_acc":
      Reference: "TW is read-only 0 when there are no modes less privileged than M;
otherwise, it must be writable."
      Current:   "csr::[tw] is read-only 0 when there are no modes less privileged than M;
otherwise, it must be writa..."
  * "norm:mstatus_tw_always_illegal":
      Reference: "An implementation may have WFI always
raise an illegal-instruction exception in modes less privilege..."
      Current:   "An implementation may have insn:wfi[] always
raise an illegal-instruction exception in modes less pr..."
  * "norm:mstatus_tw_op":
      Reference: "When TW=0, the WFI
instruction may execute in modes less privileged than M when not prevented for
so..."
      Current:   "When csr::[tw]=0, the insn:wfi[] instruction may execute in modes less privileged than M when not pr..."
  * "norm:mstatus_tw_umode_op":
      Reference: "When S-mode is implemented, then executing WFI in U-mode causes an
illegal-instruction exception, re..."
      Current:   "When S-mode is implemented, then executing insn:wfi[] in U-mode causes an
illegal-instruction except..."
  * "norm:mstatus_tw_warl":
      Reference: "The TW (Timeout Wait) bit is a WARL field that supports intercepting the WFI
instruction (see <&l..."
      Current:   "The csr::[tw] (Timeout Wait) bit is a WARL field that supports intercepting the
insn:wfi[] instructi..."
  * "norm:mstatus_ube_op":
      Reference: "If U-mode is not supported, UBE is read-only 0. Otherwise, UBE controls whether explicit load and st..."
      Current:   "If U-mode is not supported, csr::[ube] is read-only 0. Otherwise, UBE controls whether explicit load..."
  * "norm:mstatus_ube_rocopy":
      Reference: "If U-mode is supported, an implementation may make UBE be a
read-only copy of either MBE or SBE."
      Current:   "If U-mode is supported, an implementation may make csr::[ube] be a
read-only copy of either csr::[mb..."
  * "norm:mstatus_uxl_acc_mxlen64":
      Reference: "When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.
Otherwise, it is a WARL field..."
      Current:   "When MXLEN=64, if U-mode is not supported, then csr::[uxl] is read-only zero.
Otherwise, it is a WAR..."
  * "norm:mstatus_uxl_legal_vals_smode":
      Reference: "If S-mode is implemented, the set of legal values that the UXL field may assume excludes those that ..."
      Current:   "If S-mode is implemented, the set of legal values that the csr::[uxl] field may assume excludes thos..."
  * "norm:mstatus_uxl_rdonly_mxlen64":
      Reference: "an implementation may make UXL be a read-only field whose
value always ensures that UXLEN=MXLEN or U..."
      Current:   "an implementation may make csr::[uxl] be a read-only field whose
value always ensures that UXLEN=MXL..."
  * "norm:mstatus_vs_acc1":
      Reference: "If the v registers are implemented, the VS field shall not be read-only zero."
      Current:   "If the v registers are implemented, the csr::[vs] field shall not be read-only zero."
  * "norm:mstatus_vs_acc2":
      Reference: "If neither the v registers nor S-mode is implemented, then VS is
read-only zero."
      Current:   "If neither the v registers nor S-mode is implemented, then csr::[vs] is
read-only zero."
  * "norm:mstatus_vs_imprecise":
      Reference: "Implementations may choose to track the dirtiness of the vector register
state in an analogous impre..."
      Current:   "Implementations may choose to track the dirtiness of the vector register
state in an analogous impre..."
  * "norm:mstatus_vs_no_change_dirty":
      Reference: "When VS=Initial or VS=Clean, it is implementation-defined whether an
instruction that writes a vecto..."
      Current:   "When csr::[vs]=Initial or csr::[vs]=Clean, it is implementation-defined whether an
instruction that ..."
  * "norm:mstatus_vs_op":
      Reference: "The VS field encodes the status of the
vector extension state, including the vector
registers v0–v31..."
      Current:   "The csr::[vs] field encodes the status of the
vector extension state, including the vector
registers..."
  * "norm:mstatus_vs_rdonly0_s_no_v":
      Reference: "If S-mode is implemented but the v registers are not,
VS may optionally be read-only zero."
      Current:   "If S-mode is implemented but the v registers are not,
csr::[vs] may optionally be read-only zero."
  * "norm:mstatus_xret_op":
      Reference: "When executing an xRET instruction, supposing
xPP holds the value y, xIE is set to xPIE; the privile..."
      Current:   "When executing an xRET instruction, supposing
xPP holds the value y, xIE is set to xPIE; the privile..."
  * "norm:mstatus_xs_acc":
      Reference: "In harts without additional user extensions requiring new state, the
XS field is read-only zero."
      Current:   "In harts without additional user extensions requiring new state, the
csr::[xs] field is read-only ze..."
  * "norm:mstatus_xs_equiv":
      Reference: "Every additional extension with state
provides a CSR field that encodes the equivalent of the XS sta..."
      Current:   "Every additional extension with state
provides a CSR field that encodes the equivalent of the csr::[..."
  * "norm:mstatus_xs_op1":
      Reference: "The XS field encodes the status of
additional user-mode extensions and associated state."
      Current:   "The csr::[xs] field encodes the status of
additional user-mode extensions and associated state."
  * "norm:mstatus_xs_op2":
      Reference: "The XS field represents a summary of all extensions' status as shown in
<<norm:mstatus_fs_vs_x..."
      Current:   "The csr::[xs] field represents a summary of all extensions' status as shown in
<<norm:mstatus_..."
  * "norm:mstatush_enc":
      Reference: "Bits 30:4 of mstatush generally contain the same fields found in bits 62:36 of mstatus for RV64. Fie..."
      Current:   "Bits 30:4 of csr:mstatush[] generally contain the same fields found in bits 62:36 of csr:mstatus[] f..."
  * "norm:mstatush_sz_acc":
      Reference: "For RV32 only, mstatush is a 32-bit read/write register formatted as shown in <<mstatushreg&gt..."
      Current:   "For RV32 only, csr:mstatush[] is a 32-bit read/write register formatted as shown in <<mstatush..."
  * "norm:mul_op":
      Reference: "insn:mul[] performs an XLEN-bit×XLEN-bit multiplication of
rs1 by rs2 and places the lower XLEN bits..."
      Current:   "insnlink:mul[] performs an XLEN-bit×XLEN-bit multiplication of
rs1 by rs2 and places the lower XLEN ..."
  * "norm:mulh_mulhu_mulhsu_op":
      Reference: "insn:mulh[], insn:mulhu[], and insn:mulhsu[] perform the same multiplication but
return the upper XL..."
      Current:   "insnlink:mulh[], insnlink:mulhu[], and insnlink:mulhsu[] perform the same multiplication but
return ..."
  * "norm:mulw_op":
      Reference: "insn:mulw[] is an RV64 instruction that multiplies the lower 32 bits of the
source registers, placin..."
      Current:   "insnlink:mulw[] is an RV64 instruction that multiplies the lower 32 bits of the
source registers, pl..."
  * "norm:mvendorid_sz_acc_op":
      Reference: "The mvendorid CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the provider..."
      Current:   "The csr:mvendorid[] CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the pr..."
  * "norm:nop_enc":
      Reference: "insn:nop[] is encoded as insn:addi[x0,x0,0]."
      Current:   "insn:nop[] is encoded as insnlink:addi[x0,x0,0]."
  * "norm:pause_enc_fence":
      Reference: "insn:pause[] is encoded as a insn:fence[] instruction with pred=W, succ=0, fm=0,
rd=x0, and rs1=x0."
      Current:   "insnlink:pause[] is encoded as a insnlink:fence[] instruction with pred=W, succ=0, fm=0,
rd=x0, and ..."
  * "norm:pause_op":
      Reference: "The insn:pause[] instruction is a HINT that indicates the current hart's rate
of instruction retirem..."
      Current:   "The insnlink:pause[] instruction is a HINT that indicates the current hart's rate
of instruction ret..."
  * "norm:pm_uxl_clear":
      Reference: "Setting UXL/SXL/MXL to 1 will clear the corresponding pointer masking configuration bits."
      Current:   "Setting UXL/SXL to 1 will clear the corresponding pointer masking configuration bits."
  * "norm:prefetch-i_op":
      Reference: "A insn:prefetch.i[] instruction indicates to hardware that the cache block whose effective address i..."
      Current:   "A insnprefetch.i instruction indicates to hardware that the cache block whose effective address is t..."
  * "norm:prefetch-r_op":
      Reference: "A insn:prefetch.r[] instruction indicates to hardware that the cache block whose effective address i..."
      Current:   "A insnprefetch.r instruction indicates to hardware that the cache block whose effective address is t..."
  * "norm:prefetch-w_op":
      Reference: "A insn:prefetch.w[] instruction indicates to hardware that the cache block whose effective address i..."
      Current:   "A insnprefetch.w instruction indicates to hardware that the cache block whose effective address is t..."
  * "norm:rem_remu_op":
      Reference: "insn:rem[] and insn:remu[]
provide the remainder of the corresponding division operation."
      Current:   "insnlink:rem[] and insnlink:remu[]
provide the remainder of the corresponding division operation."
  * "norm:rem_result_sign":
      Reference: "For insn:rem[],
the sign of a nonzero result equals the sign of the dividend."
      Current:   "For insnlink:rem[],
the sign of a nonzero result equals the sign of the dividend."
  * "norm:remw_remuw_op":
      Reference: "insn:remw[] and insn:remuw[] are RV64 instructions that
provide the corresponding signed and unsigne..."
      Current:   "insnlink:remw[] and insnlink:remuw[] are RV64 instructions that
provide the corresponding signed and..."
  * "norm:remw_remuw_result_sign":
      Reference: "Both insn:remw[] and insn:remuw[] always sign-extend the 32-bit result
to 64 bits, including on a di..."
      Current:   "Both insnlink:remw[] and insnlink:remuw[] always sign-extend the 32-bit result
to 64 bits, including..."
  * "norm:rv32_ssamoswap-w_op":
      Reference: "For RV32, insn:ssamoswap.w[] atomically loads a 32-bit data value from address of a shadow stack loc..."
      Current:   "For RV32, insnssamoswap.w atomically loads a 32-bit data value from address of a shadow stack locati..."
  * "norm:rv64_ssamoswap-w_op":
      Reference: "For RV64, insn:ssamoswap.w[] atomically loads a 32-bit data value from address of a shadow stack loc..."
      Current:   "For RV64, insnssamoswap.w atomically loads a 32-bit data value from address of a shadow stack locati..."
  * "norm:rvwmo_only_mainmem":
      Reference: "This chapter defines the memory model for regular main memory
operations. The interaction of the mem..."
      Current:   "This chapter defines the memory model for regular main memory
operations. The interaction of the mem..."
  * "norm:rvwmo_ppo_sync1":
      Reference: "There is a insn:fence[] instruction that orders a before b"
      Current:   "There is a insnlink:fence[] instruction that orders a before b"
  * "norm:sc_failed_as_store":
      Reference: "For the purposes of memory protection, a failed insn:sc.w[] may be
treated like a store."
      Current:   "For the purposes of memory protection, a failed insnlink:sc.w[] may be
treated like a store."
  * "norm:sc_failed_side_effects":
      Reference: "but it is UNSPECIFIED whether any side effects of implicit address translation
and protection memory..."
      Current:   "but it is UNSPECIFIED whether any side effects of implicit address translation
and protection memory..."
  * "norm:sc_reservation_invalidate":
      Reference: "Regardless of success or failure, executing an
insn:sc.w[] instruction invalidates any reservation h..."
      Current:   "Regardless of success or failure, executing an
insnlink:sc.w[] instruction invalidates any reservati..."
  * "norm:sc_retire_permission":
      Reference: "No insn:sc.w[] instruction shall retire unless it passes memory permission checks,"
      Current:   "No insnlink:sc.w[] instruction shall retire unless it passes memory permission checks,"
  * "norm:sc_w_failure":
      Reference: "If the insn:sc.w[] fails,
the instruction does not write to memory, and it writes a nonzero value
to..."
      Current:   "If the insnlink:sc.w[] fails,
the instruction does not write to memory, and it writes a nonzero valu..."
  * "norm:sc_w_success":
      Reference: "insn:sc.w[] conditionally
writes a word in rs2 to the address in rs1: the insn:sc.w[] succeeds only
..."
      Current:   "insnlink:sc.w[] conditionally
writes a word in rs2 to the address in rs1: the insnlink:sc.w[] succee..."
  * "norm:sd_sw_sh_sb_op_rv64i":
      Reference: "The insn:sd[], insn:sw[], insn:sh[], and insn:sb[] instructions
store 64-bit, 32-bit, 16-bit, and 8-..."
      Current:   "The insnlink:sd[], insnlink:sw[], insnlink:sh[], and insnlink:sb[] instructions
store 64-bit, 32-bit..."
  * "norm:seed_ro_illegal":
      Reference: "Attempts to access the csr:seed[] CSR using a read-only CSR-access instruction
(insn:csrrs[]/insn:cs..."
      Current:   "Attempts to access the csr:seed[] CSR using a read-only CSR-access instruction
(insnlink:csrrs[]/ins..."
  * "norm:sll_srl_sra_op":
      Reference: "insn:sll[], insn:srl[], and insn:sra[] perform logical left, logical right, and arithmetic
right shi..."
      Current:   "insnlink:sll[], insnlink:srl[], and insnlink:sra[] perform logical left, logical right, and arithmet..."
  * "norm:slli_op":
      Reference: "insn:slli[] is a logical left shift (zeros are shifted into the lower bits);"
      Current:   "insnlink:slli[] is a logical left shift (zeros are shifted into the lower bits);"
  * "norm:slliw_srliw_sraiw_imm5_rsv":
      Reference: "insn:slliw[], insn:srliw[], and insn:sraiw[] encodings with
imm[5]{ne}0 are reserved."
      Current:   "insnlink:slliw[], insnlink:srliw[], and insnlink:sraiw[] encodings with
imm[5]{ne}0 are reserved."
  * "norm:slliw_srliw_sraiw_op":
      Reference: "insn:slliw[], insn:srliw[], and insn:sraiw[] are RV64I-only instructions that are analogously
define..."
      Current:   "insnlink:slliw[], insnlink:srliw[], and insnlink:sraiw[] are RV64I-only instructions that are analog..."
  * "norm:sllw_srlw_sraw_op":
      Reference: "insn:sllw[], insn:srlw[], and insn:sraw[] are RV64I-only instructions that are analogously defined b..."
      Current:   "insnsllw, insnsrlw, and insnsraw are RV64I-only instructions that are analogously defined but operat..."
  * "norm:slt_sltu_op":
      Reference: "insn:slt[] and insn:sltu[] perform signed and unsigned compares respectively, writing 1 to rd if
rs1..."
      Current:   "insnlink:slt[] and insnlink:sltu[] perform signed and unsigned compares respectively, writing 1 to r..."
  * "norm:slti_sltiu_op":
      Reference: "insn:slti[] (set less than immediate) places the value 1 in register rd if
register rs1 is less than..."
      Current:   "insnlink:slti[] (set less than immediate) places the value 1 in register rd if
register rs1 is less ..."
  * "norm:srai_op":
      Reference: "insn:srai[] is an arithmetic right shift (the original sign bit is copied into the vacated upper bit..."
      Current:   "insnlink:srai[] is an arithmetic right shift (the original sign bit is copied into the vacated upper..."
  * "norm:srli_op":
      Reference: "insn:srli[] is a logical right shift (zeros are shifted into the upper bits);"
      Current:   "insnlink:srli[] is a logical right shift (zeros are shifted into the upper bits);"
  * "norm:ssamoswap_address":
      Reference: "Just as for AMOs in the ext:a[] extension, insn:ssamoswap.w[] or insn:ssamoswap.d[] requires that th..."
      Current:   "Just as for AMOs in the ext:a[] extension, insnssamoswap.w or insnssamoswap.d requires that the addr..."
  * "norm:ssmp_ss_idempotent_memory":
      Reference: "If the memory referenced by
insn:sspush[], insn:c.sspush[], insn:sspopchk[], insn:c.sspopchk[], insn..."
      Current:   "If the memory referenced by
insn:sspush[], insn:c.sspush[], insn:sspopchk[], insn:c.sspopchk[], insn..."
  * "norm:ssmp_ss_page_access_fault":
      Reference: "Memory mapped as an SS page cannot be written to by instructions other than
insn:ssamoswap.w[], insn..."
      Current:   "Memory mapped as an SS page cannot be written to by instructions other than
insnlink:ssamoswap.w[], ..."
  * "norm:ssmp_ssamoswap":
      Reference: "When the effective privilege mode is M, memory access
by an insn:ssamoswap.w[] or insn:ssamoswap.d[]..."
      Current:   "When the effective privilege mode is M, memory access
by an insnlink:ssamoswap.w[] or insnlink:ssamo..."
  * "norm:ssrdp_read":
      Reference: "The insn:ssrdp[] instruction is provided to move the contents of csr:ssp[] to a destination register..."
      Current:   "The insnssrdp instruction is provided to move the contents of csr:ssp[] to a destination register."
  * "norm:sstatus_sdt_clr_mnret":
      Reference: "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then ssta..."
      Current:   "If the ext:ssdbltrp[] extension is also implemented, and the new privilege mode is U, VS, or VU, the..."
  * "norm:sstatus_sdt_clr_mret_sret":
      Reference: "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then ssta..."
      Current:   "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then csr:..."
  * "norm:sub_op":
      Reference: "insn:sub[] performs the subtraction of rs2 from rs1."
      Current:   "insnlink:sub[] performs the subtraction of rs2 from rs1."
  * "norm:sw_sh_sb_op":
      Reference: "The insn:sw[], insn:sh[], and insn:sb[] instructions store 32-bit, 16-bit, and
8-bit values from the..."
      Current:   "The insnlink:sw[], insnlink:sh[], and insnlink:sb[] instructions store 32-bit, 16-bit, and
8-bit val..."
  * "norm:trap_exp":
      Reference: "When a trap is to be taken into M-mode, if the MDT bit is currently 0, it is then set to 1, and the ..."
      Current:   "When a trap is to be taken into M-mode, if the csr::[mdt] bit is currently 0, it is then set to 1, a..."
  * "norm:trap_unexp_hndl_no_rnmi":
      Reference: "When the Smrnmi extension is not implemented, or if the Smrnmi extension is
implemented and mnstatus..."
      Current:   "When the ext:smrnmi[] extension is not implemented, or if the ext:smrnmi[] extension is
implemented ..."
  * "norm:trap_unexp_hndl_rnmi":
      Reference: "When the Smrnmi extension is implemented and mnstatus.NMIE is 1, the hart
traps to the RNMI handler...."
      Current:   "When the Smrnmi extension is implemented and csr:mnstatus[nmie] is 1, the hart
traps to the RNMI han..."
  * "norm:trap_unexp_mdt_1":
      Reference: "However, if MDT is already set to 1, then this is an unexpected trap."
      Current:   "However, if csr::[mdt] is already set to 1, then this is an unexpected trap."
  * "norm:trap_unexp_mnstatus_nmie_0":
      Reference: "a trap that occurs when executing in M-mode with
mnstatus.NMIE set to 0 is an unexpected trap."
      Current:   "a trap that occurs when executing in M-mode with
csr:mnstatus[nmie] set to 0 is an unexpected trap."
  * "norm:trap_unexp_rnmi":
      Reference: "When the Smrnmi extension
is implemented, a trap caused by an RNMI is not considered an unexpected t..."
      Current:   "When the ext:smrnmi[] extension
is implemented, a trap caused by an RNMI is not considered an unexpe..."
  * "norm:vcpop_op":
      Reference: "The insn:vcpop.m[] instruction counts the number of mask elements of the
active elements of the vect..."
      Current:   "The insnlink:vcpop.m[] instruction counts the number of mask elements of the
active elements of the ..."
  * "norm:vcpop_trap":
      Reference: "Traps on insn:vcpop.m[] are always reported with a csr:vstart[] of 0."
      Current:   "Traps on insnlink:vcpop.m[] are always reported with a csr:vstart[] of 0."
  * "norm:vcpop_vl0":
      Reference: "The insn:vcpop.m[] instruction writes x[rd] even if csr:vl[]=0 (with the
value 0, since no mask elem..."
      Current:   "The insnlink:vcpop.m[] instruction writes x[rd] even if csr:vl[]=0 (with the
value 0, since no mask ..."
  * "norm:vfirst_vl0":
      Reference: "The insn:vfirst.m[] instruction writes x[rd] even if vl=0 (with the
value -1, since no mask elements..."
      Current:   "The insnlink:vfirst.m[] instruction writes x[rd] even if vl=0 (with the
value -1, since no mask elem..."
  * "norm:vfmv-f-s_op":
      Reference: "The insn:vfmv.f.s[] instruction copies a single SEW-wide element from index
0 of the source vector r..."
      Current:   "The insnlink:vfmv.f.s[] instruction copies a single SEW-wide element from index
0 of the source vect..."
  * "norm:vfmv-s-f_masked_rsv":
      Reference: "The encodings corresponding to the masked versions (vm=0) of
insn:vfmv.f.s[] and insn:vfmv.s.f[] are..."
      Current:   "The encodings corresponding to the masked versions (vm=0) of
insnlink:vfmv.f.s[] and insnlink:vfmv.s..."
  * "norm:vfmv-s-f_op":
      Reference: "The insn:vfmv.s.f[] instruction copies the scalar floating-point register
to element 0 of the destin..."
      Current:   "The insnlink:vfmv.s.f[] instruction copies the scalar floating-point register
to element 0 of the de..."
  * "norm:vfsqrt_op":
      Reference: "The insn:vfsqrt.v[] instruction is a unary vector-vector instruction."
      Current:   "The insnvfsqrt.v instruction is a unary vector-vector instruction."
  * "norm:vid_op":
      Reference: "The insn:vid.v[] instruction writes each element's index to the
destination vector register group, f..."
      Current:   "The insnlink:vid.v[] instruction writes each element's index to the
destination vector register grou..."
  * "norm:viota_op":
      Reference: "The insn:viota.m[] instruction reads a source vector mask register and
writes to each element of the..."
      Current:   "The insnlink:viota.m[] instruction reads a source vector mask register and
writes to each element of..."
  * "norm:viota_trap":
      Reference: "Traps on insn:viota.m[] are always reported with a csr:vstart[] of 0,"
      Current:   "Traps on insnlink:viota.m[] are always reported with a csr:vstart[] of 0,"
  * "norm:vmsbf_op":
      Reference: "The insn:vmsbf.m[] instruction takes a mask register as input and writes
results to a mask register...."
      Current:   "The insnlink:vmsbf.m[] instruction takes a mask register as input and writes
results to a mask regis..."
  * "norm:vmsbf_trap":
      Reference: "Traps on insn:vmsbf.m[] are always reported with a csr:vstart[] of 0."
      Current:   "Traps on insnlink:vmsbf.m[] are always reported with a csr:vstart[] of 0."
  * "norm:vmsbf_vstart_n0_ill":
      Reference: "The
insn:vmsbf.m[] instruction will raise an illegal-instruction exception if
csr:vstart[] is non-ze..."
      Current:   "The
insnlink:vmsbf.m[] instruction will raise an illegal-instruction exception if
csr:vstart[] is no..."
  * "norm:vmsif_trap":
      Reference: "Traps on insn:vmsif.m[] are always reported with a csr:vstart[] of 0."
      Current:   "Traps on insnlink:vmsif.m[] are always reported with a csr:vstart[] of 0."
  * "norm:vmsif_vstart_n0_ill":
      Reference: "The
insn:vmsif.m[] instruction will raise an illegal-instruction exception if
csr:vstart[] is non-ze..."
      Current:   "The
insnlink:vmsif.m[] instruction will raise an illegal-instruction exception if
csr:vstart[] is no..."
  * "norm:vmsof_trap":
      Reference: "Traps on insn:vmsof.m[] are always reported with a vstart of 0."
      Current:   "Traps on insnlink:vmsof.m[] are always reported with a vstart of 0."
  * "norm:vmsof_vstart_n0_ill":
      Reference: "The
insn:vmsof.m[] instruction will raise an illegal-instruction exception if
csr:vstart[] is non-ze..."
      Current:   "The
insnlink:vmsof.m[] instruction will raise an illegal-instruction exception if
csr:vstart[] is no..."
  * "norm:vmv-s-x_op":
      Reference: "The insn:vmv.s.x[] instruction copies the scalar integer register to element 0 of
the destination ve..."
      Current:   "The insnlink:vmv.s.x[] instruction copies the scalar integer register to element 0 of
the destinatio..."
  * "norm:vmv-s-x_vmv-x-s_masked_rsv":
      Reference: "The encodings corresponding to the masked versions (vm=0) of
insn:vmv.x.s[] and insn:vmv.s.x[] are r..."
      Current:   "The encodings corresponding to the masked versions (vm=0) of
insnlink:vmv.x.s[] and insnlink:vmv.s.x..."
  * "norm:vmv-x-s_op":
      Reference: "The insn:vmv.x.s[] instruction copies a single SEW-wide element from index 0 of the
source vector re..."
      Current:   "The insnlink:vmv.x.s[] instruction copies a single SEW-wide element from index 0 of the
source vecto..."
  * "norm:vmv-x-s_vstartgevl_vl0":
      Reference: "insn:vmv.x.s[] performs its operation even if csr:vstart[] {ge} csr:vl[] or csr:vl[]=0."
      Current:   "insnlink:vmv.x.s[] performs its operation even if csr:vstart[] {ge} csr:vl[] or csr:vl[]=0."
  * "norm:vmv_op":
      Reference: "The vector integer move instructions copy a source operand to a vector
register group.
The insn:vmv...."
      Current:   "The vector integer move instructions copy a source operand to a vector
register group.
The insnlink:..."
  * "norm:vnsrl_vnsra_op":
      Reference: "The narrowing right shifts extract a smaller field from a wider
operand and have both zero-extending..."
      Current:   "The narrowing right shifts extract a smaller field from a wider
operand and have both zero-extending..."
  * "norm:vreg_mask_tail_op":
      Reference: "In addition, except for mask load instructions, any element in the tail of a mask result can also be..."
      Current:   "In addition, except for mask load instructions, any element in the tail of a mask result can also be..."
  * "norm:vrgather-vv_sew_lmul":
      Reference: "The insn:vrgather.vv[] form uses SEW/LMUL for both the data and
indices."
      Current:   "The insnlink:vrgather.vv[] form uses SEW/LMUL for both the data and
indices."
  * "norm:vrgatherei16-vv_sew_lmul":
      Reference: "The insn:vrgatherei16.vv[] form uses SEW/LMUL for the data in
vs2 but EEW=16 and EMUL = (16/SEW)*LMU..."
      Current:   "The insnlink:vrgatherei16.vv[] form uses SEW/LMUL for the data in
vs2 but EEW=16 and EMUL = (16/SEW)..."
  * "norm:vset_op":
      Reference: "The
insn:vsetvli[], insn:vsetivli[], and insn:vsetvl[] instructions set the csr:vtype[] and csr:vl[]..."
      Current:   "The
insnlink:vsetvli[], insnlink:vsetivli[], and insnlink:vsetvl[] instructions set the csr:vtype[] ..."
  * "norm:vsetivli_op":
      Reference: "For the insn:vsetivli[] instruction, the AVL is encoded as a 5-bit zero-extended immediate (0—..."
      Current:   "For the insnvsetivli instruction, the AVL is encoded as a 5-bit zero-extended immediate (0—&#8..."
  * "norm:vsll_vsrl_vsra_op":
      Reference: "A full set of vector shift instructions are provided, including
logical shift left (insn:sll[]), and..."
      Current:   "A full set of vector shift instructions are provided, including
logical shift left (insnlink:sll[]),..."
  * "norm:vsstatus_sdt_clr_mnret":
      Reference: "Additionally, if it is VU, then vsstatus.SDT is also set to 0."
      Current:   "Additionally, if it is VU, then csr:vsstatus[sdt] is also set to 0."
  * "norm:vsstatus_sdt_clr_mret_sret":
      Reference: "Additionally, if it is VU, then vsstatus.SDT is also set to 0."
      Current:   "Additionally, if it is VU, then csr:vsstatus[sdt] is also set to 0."
  * "norm:vtype_acc":
      Reference: "The new csr:vtype[] value is encoded in the immediate fields of insn:vsetvli[] and insn:vsetivli[], ..."
      Current:   "The new csr:vtype[] value is encoded in the immediate fields of insnvsetvli and insnvsetivli, and in..."
  * "norm:vtype_sz_acc_op":
      Reference: "The read-only XLEN-wide vector type CSR, csr:vtype[] provides the
default type used to interpret the..."
      Current:   "The read-only XLEN-wide vector type CSR, csr:vtype[] provides the
default type used to interpret the..."
  * "norm:vwredsum_op":
      Reference: "The insn:vwredsum.vs[] instruction sign-extends the SEW-wide vector
elements before summing them."
      Current:   "The insnlink:vwredsum.vs[] instruction sign-extends the SEW-wide vector
elements before summing them..."
  * "norm:vwredsumu_op":
      Reference: "The unsigned insn:vwredsumu.vs[] instruction zero-extends the SEW-wide
vector elements before summin..."
      Current:   "The unsigned insnlink:vwredsumu.vs[] instruction zero-extends the SEW-wide
vector elements before su..."
  * "norm:vwredsumu_vwredsum_op_overflow":
      Reference: "For both insn:vwredsumu.vs[] and insn:vwredsum.vs[], overflows wrap around."
      Current:   "For both insnlink:vwredsumu.vs[] and insnlink:vwredsum.vs[], overflows wrap around."
  * "norm:xlen_reduction_hint_op1":
      Reference: "Some HINT instructions are encoded as integer computational instructions that overwrite their destin..."
      Current:   "Some HINT instructions are encoded as integer computational instructions that overwrite their destin..."
  * "norm:zbb_orc_b_semantics":
      Reference: "insn:orc.b[] sets the bits of each byte in the result rd to all zeros if no bit within the respectiv..."
      Current:   "insnlink:orc.b[] sets the bits of each byte in the result rd to all zeros if no bit within the respe..."
  * "norm:zbc_clmul_clmulh_results":
      Reference: "insn:clmul[] produces the lower half of the carry-less product and insn:clmulh[] produces the upper ..."
      Current:   "insnlink:clmul[] produces the lower half of the carry-less product and insnlink:clmulh[] produces th..."
  * "norm:zbc_clmulr_results":
      Reference: "insn:clmulr[] produces bits 2{times}XLEN−2:XLEN-1 of the 2{times}XLEN carry-less product."
      Current:   "insnlink:clmulr[] produces bits 2{times}XLEN−2:XLEN-1 of the 2{times}XLEN carry-less product."
  * "norm:zfhmin":
      Reference: "The ext:zfhmin[] extension includes the following instructions from the ext:zfh[] extension: insn:fl..."
      Current:   "The ext:zfhmin[] extension includes the following instructions from the ext:zfh[] extension: insnflh..."
  * "norm:zicfiss_c-sspopchk_enc":
      Reference: "insn:c.sspopchk[x5] - encoded using insn:c.mop.5[]"
      Current:   "insn:c.sspopchk[x5] - encoded using insnlink:c.mop.5[]"
  * "norm:zicfiss_c-sspush_enc":
      Reference: "insn:c.sspush[x1] - encoded using insn:c.mop.1[]"
      Current:   "insn:c.sspush[x1] - encoded using insnlink:c.mop.1[]"
  * "norm:zicfiss_enc":
      Reference: "The ext:zicfiss[] instructions, except insn:ssamoswap.w[] and insn:ssamoswap.d[], are encoded using ..."
      Current:   "The ext:zicfiss[] instructions, except insnlink:ssamoswap.w[] and insnlink:ssamoswap.d[], are encode..."
  * "norm:zicfiss_sspopchk_enc":
      Reference: "insn:sspopchk[x1] and insn:sspopchk[x5] - encoded using insn:mop.r.28[]"
      Current:   "insn:sspopchk[x1] and insn:sspopchk[x5] - encoded using insnlink:mop.r.28[]"
  * "norm:zicfiss_sspush_enc":
      Reference: "insn:sspush[x1] and insn:sspush[x5] - encoded using insn:mop.rr.7[]"
      Current:   "insn:sspush[x1] and insn:sspush[x5] - encoded using insnlink:mop.rr.7[]"
  * "norm:zicfiss_ssrdp_enc":
      Reference: "insn:ssrdp[] - encoded using insn:mop.r.28[]"
      Current:   "insnlink:ssrdp[] - encoded using insnlink:mop.r.28[]"
  * "norm:zicflip_elp_lpad_expected":
      Reference: "When ELP is set to LP_EXPECTED, if the next instruction in the instruction stream is not 4-byte alig..."
      Current:   "When ELP is set to LP_EXPECTED, if the next instruction in the instruction stream is not 4-byte alig..."
  * "norm:zicflip_indirect_branch_lpad":
      Reference: "An indirect branch using insn:jalr[], insn:c.jalr[], or insn:c.jr[] with rs1 as x7 is termed a softw..."
      Current:   "An indirect branch using insnjalr, insnc.jalr, or insnc.jr with rs1 as x7 is termed a software-guard..."
  * "norm:zicflip_lpad_enabled_exception":
      Reference: "If ext:zicfilp[] is enabled, the insn:lpad[] instruction causes a
software-check exception with xtva..."
      Current:   "If ext:zicfilp[] is enabled, the insnlink:lpad[] instruction causes a
software-check exception with ..."
  * "norm:zicflip_lpad_enabled_instr_allowed":
      Reference: "When ext:zicfilp[] is enabled, insn:lpad[] is the only instruction allowed to execute when
the ELP s..."
      Current:   "When ext:zicfilp[] is enabled, insnlink:lpad[] is the only instruction allowed to execute when
the E..."
  * "norm:zicflip_lpad_enc":
      Reference: "The insn:lpad[] instruction (See <<LP_INST>>) is
encoded using the insn:auipc[] major op..."
      Current:   "The insnlink:lpad[] instruction (See <<LP_INST>>) is
encoded using the insnlink:auipc[] ..."
  * "norm:zicflip_lpad_imm_enc":
      Reference: "The insn:lpad[] instruction is encoded with a
20-bit immediate value called the landing-pad-label (L..."
      Current:   "The insnlink:lpad[] instruction is encoded with a
20-bit immediate value called the landing-pad-labe..."
  * "norm:zicflip_lpad_label":
      Reference: "To support labeled landing pads, the
indirect call/jump sites establish an expected landing pad labe..."
      Current:   "To support labeled landing pads, the
indirect call/jump sites establish an expected landing pad labe..."
  * "norm:zknd_shared_instr":
      Reference: "The insn:aes64ks1i[] and insn:aes64ks2[] instructions
are present in both the extlink:zknd[] and ext..."
      Current:   "The insnlink:aes64ks1i[] and insnlink:aes64ks2[] instructions
are present in both the extlink:zknd[]..."
  * "norm:zkne_shared_instr":
      Reference: "The insn:aes64ks1i[] and insn:aes64ks2[] instructions
are present in both the extlink:zknd[] and ext..."
      Current:   "The insnlink:aes64ks1i[] and insnlink:aes64ks2[] instructions
are present in both the extlink:zknd[]..."

================================================================================
Summary: 448 total changes
  Added:    0
  Deleted:  2
  Modified: 446
================================================================================

---

What happens next:

• This comment is informational only and does not block merging
• When this PR is merged, a GitHub issue will be automatically created with the NormRules label for CSC tracking
• If these changes are unintentional, please update the PR before merging

How to update reference files (if needed):

make update-ref
git add ref/*.json
git commit -m "Update normative tag reference files"

Note: New tags (additions) are automatically added to the reference files when PRs are merged to main. Only modifications and deletions require manual review.

This comment was automatically generated by the normative tag check workflow.

[Andrew Waterman (aswaterman)]

Bill Traynor (@wmat) Thank you. I am playing around with an alternate scheme to generate these from UDB as part of the spec build process, rather than committing the compiled result. It might not pan out, in which case this route is OK. Let's sit on this for now.

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[Bill Traynor (wmat)]

Sounds good. Note that I have a PR to UDB as well that splits the single adoc file.

In the meantime, I'll clean up the check failures.

[Bill Traynor (wmat)]

Also, the script I've pushed to UDB can be easily automated. I didn't immediately do it as I wanted to ensure the ISA docs were good.

[Andrew Waterman (aswaterman)]

Yeah, whichever approach we take, we'll want to automate it. Give me some time to keep pushing on my scheme and then we can decide.

[github-actions]

:warning: DCO CHECK FAILED :warning:

The Developer's Certificate of Origin (DCO) check has failed for this pull request.
To fix this, you need to sign off on your commits.

For instructions on how to set up signed commits, please see:
https://github.com/riscv/docs-spec-template/blob/main/CONTRIBUTING.md

Once you have signed your commits, you will need to force-push your changes.

[github-actions]

:warning: DCO CHECK FAILED :warning:

The Developer's Certificate of Origin (DCO) check has failed for this pull request.
To fix this, you need to sign off on your commits.

For instructions on how to set up signed commits, please see:
https://github.com/riscv/docs-spec-template/blob/main/CONTRIBUTING.md

Once you have signed your commits, you will need to force-push your changes.

[Bill Traynor (wmat)]

Andrew Waterman (@aswaterman) fixed up the DCO Check failure so once the Build ISA completes the artifacts will be available. Note that the instructions in the body of the books will link to their single page description in their respective books. This means that something like ADD will reside in both Unpriv and Priv indexes. This is OK though, as those indexes are generated from UDB's single all_instructions.adoc file, not manually added twice.

Also, with the additions of theses indexes the ISA build step takes 1-2 an hours, so that will need considerable improvement.

[Andrew Waterman (aswaterman)]

Bill Traynor (@wmat) While I continue working on the generation aspect, can you research where all the runtime is going and start looking into solutions to improve it?

[Bill Traynor (wmat)]

Will do.