Fix bit-manipulation reference pseudocode

[Abhinav Agarwal (abhinavagarwal07)]

This fixes a few small mistakes in the bit-manipulation reference pseudocode:

• stop the brev8 and xperm8/xperm4 loops at the last in-range byte/nibble
• make clzw call the 32-bit helper it defines, instead of the XLEN-wide helper
• make the ctz/ctzw loops count upward, matching the prose and the cpop/cpopw pattern

These are text/pseudocode corrections only; they do not change the intended architectural behavior.

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This PR modifies normatively tagged text. Please review the changes below to ensure they are intentional.

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Normative Tag Change Report

riscv-spec Specification

================================================================================
Tag Changes Report
================================================================================

Reference file: ref/riscv-spec-norm-tags.json
Current file: build/riscv-spec-norm-tags.json
Deleted 2 tags:
  * "norm:pm_family_extensions": "Pointer masking refers to a number of separate extensions, all of which are privileged."
  * "norm:pm_tag_check_impl": "The tag checks themselves can be implemented in software or hardware."

Modified 173 tags:
  * "norm:Zawrs_wrs-sto_stall_duration":
      Reference: "insn:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insn:wrs.nto[] but bounds the st..."
      Current:   "insn:wrs.sto[] (WRS-with-short-timeout) is
provided that works like insn:wrs.nto[] but bounds the st..."
  * "norm:intr_mip_mie_bounded_time":
      Reference: "These conditions for an interrupt trap to occur must be evaluated in a
bounded amount of time from w..."
      Current:   "These conditions for an interrupt trap to occur must be evaluated in a
bounded amount of time from w..."
  * "norm:intr_mip_mie_op":
      Reference: "An interrupt i will trap to M-mode (causing the privilege mode to
change to M-mode) if all of the fo..."
      Current:   "An interrupt i will trap to M-mode (causing the privilege mode to
change to M-mode) if all of the fo..."
  * "norm:intr_mip_mie_xret_csrwr":
      Reference: "be evaluated immediately following the
execution of an xRET instruction or an explicit write to a CS..."
      Current:   "be evaluated immediately following the
execution of an xRET instruction or an explicit write to a CS..."
  * "norm:intr_sei_op":
      Reference: "Supervisor-level external interrupts are made pending based on the logical-OR of the
software-writab..."
      Current:   "Supervisor-level external interrupts are made pending based on the logical-OR of the
software-writab..."
  * "norm:marchid_sz_acc_op":
      Reference: "The marchid CSR is an MXLEN-bit read-only register encoding the base
microarchitecture of the hart."
      Current:   "The csr:marchid[] CSR is an MXLEN-bit read-only register encoding the base
microarchitecture of the ..."
  * "norm:medeleg_16_no_rd0":
      Reference: "The medeleg[16] is read-only zero as double trap is not delegatable."
      Current:   "The csr:medeleg[][16] is read-only zero as double trap is not delegatable."
  * "norm:medeleg_enc_txt":
      Reference: "medeleg has a bit position allocated for every synchronous exception
shown in <<norm:mcause_ex..."
      Current:   "csr:medeleg[] has a bit position allocated for every synchronous exception
shown in <<norm:mca..."
  * "norm:medeleg_mideleg_omit_wo_S_mode":
      Reference: "In harts without S-mode, the medeleg and mideleg registers should not exist."
      Current:   "In harts without S-mode, the csr:medeleg[] and csr:mideleg[] registers should not exist."
  * "norm:medeleg_mideleg_op1":
      Reference: "implementations can provide individual read/write bits within medeleg
and mideleg to indicate that c..."
      Current:   "implementations can provide individual read/write bits within
csr:medeleg[] and csr:mideleg[] to ind..."
  * "norm:medeleg_mideleg_op2":
      Reference: "setting a bit in medeleg or mideleg will delegate the
corresponding trap, when occurring in S-mode o..."
      Current:   "setting a bit in csr:medeleg[] or csr:mideleg[] will delegate the
corresponding trap, when occurring..."
  * "norm:medeleg_mideleg_warl":
      Reference: "An implementation can choose to subset the delegatable traps, with the
supported delegatable bits fo..."
      Current:   "An implementation can choose to subset the delegatable traps, with the
supported delegatable bits fo..."
  * "norm:medeleg_no_rd1":
      Reference: "An implementation shall not have any bits of medeleg be read-only one"
      Current:   "An implementation shall not have any bits of csr:medeleg[] be read-only one"
  * "norm:medeleg_sz_acc":
      Reference: "The machine exception delegation register (medeleg) is a 64-bit read/write register."
      Current:   "The machine exception delegation register (csr:medeleg[]) is a 64-bit read/write register."
  * "norm:medeleg_when_rd0":
      Reference: "For exceptions that cannot occur in less privileged modes, the
corresponding medeleg bits should be ..."
      Current:   "For exceptions that cannot occur in less privileged modes, the
corresponding csr:medeleg[] bits shou..."
  * "norm:medelegh_omit_xlen64":
      Reference: "The medelegh register does not exist when XLEN=64."
      Current:   "The csr:medelegh[] register does not exist when XLEN=64."
  * "norm:medelegh_sz_acc_enc_xlen32":
      Reference: "When XLEN=32, medelegh is a 32-bit read/write register
that aliases bits 63:32 of medeleg."
      Current:   "When XLEN=32, csr:medelegh[] is a 32-bit read/write register
that aliases bits 63:32 of csr:medeleg[..."
  * "norm:mhartid_sz_acc_op":
      Reference: "The mhartid CSR is an MXLEN-bit read-only register containing the
integer ID of the hardware thread ..."
      Current:   "The csr:mhartid[] CSR is an MXLEN-bit read-only register containing the
integer ID of the hardware t..."
  * "norm:mideleg_enc_txt":
      Reference: "mideleg holds trap delegation bits for individual interrupts, with the
layout of bits matching those..."
      Current:   "csr:mideleg[] holds trap delegation bits for individual interrupts, with the
layout of bits matching..."
  * "norm:mideleg_no_rd1":
      Reference: "an implementation shall not fix as read-only one
any bits of mideleg corresponding to machine-level ..."
      Current:   "an implementation shall not fix as read-only one
any bits of csr:mideleg[] corresponding to machine-..."
  * "norm:mideleg_sz_acc":
      Reference: "The machine interrupt delegation (mideleg) register is an MXLEN-bit
read/write register."
      Current:   "The machine interrupt delegation (csr:mideleg[]) register is an MXLEN-bit
read/write register."
  * "norm:mie_bits_rdonly0":
      Reference: "Bits of mie that are not writable must be read-only zero."
      Current:   "Bits of csr:mie[] that are not writable must be read-only zero."
  * "norm:mie_bits_wr":
      Reference: "The mie register must always be implemented.
A bit in mie must be writable if the corresponding inte..."
      Current:   "The csr:mie[] register must always be implemented.
A bit in csr:mie[] must be writable if the corres..."
  * "norm:mie_sz_acc":
      Reference: "mie is the corresponding
MXLEN-bit read/write register containing interrupt enable bits."
      Current:   "csr:mie[] is the corresponding
MXLEN-bit read/write register containing interrupt enable bits."
  * "norm:mimpid_op":
      Reference: "The mimpid CSR provides a unique encoding of the version of the
processor implementation."
      Current:   "The csr:mimpid[] CSR provides a unique encoding of the version of the
processor implementation."
  * "norm:mip_bits_rdonly_op":
      Reference: "If interrupt i can become pending but bit i in mip is read-only, the implementation must
provide som..."
      Current:   "If interrupt i can become pending but bit i in csr:mip[] is read-only, the implementation must
provi..."
  * "norm:mip_bits_wr_op":
      Reference: "When bit i in mip is writable, a pending interrupt i
can be cleared by writing 0 to this bit."
      Current:   "When bit i in csr:mip[] is writable, a pending interrupt i
can be cleared by writing 0 to this bit."
  * "norm:mip_bits_wr_or_rdonly":
      Reference: "The mip register must always be implemented,
but can contain read-only zeros in any position, indica..."
      Current:   "The csr:mip[] register must always be implemented,
but can contain read-only zeros in any position, ..."
  * "norm:mip_lcofip_acc":
      Reference: "LCOFIP is read-write in mip"
      Current:   "csr::[lcofip] is read-write in csr:mip[]"
  * "norm:mip_lcofip_mie_lcofie_op":
      Reference: "If the Sscofpmf extension is implemented, bits mip.LCOFIP and mie.LCOFIE
are the interrupt-pending a..."
      Current:   "If the ext:sscofpmf[] extension is implemented, bits csr:mip[lcofip] and
csr:mie[lcofie] are the int..."
  * "norm:mip_lcofip_mie_lcofie_rdonly0":
      Reference: "If the Sscofpmf extension is not implemented, mip.LCOFIP and mie.LCOFIE are
read-only zeros."
      Current:   "If the ext:sscofpmf[] extension is not implemented, csr:mip[lcofip] and csr:mie[lcofie] are
read-onl..."
  * "norm:mip_meip_mie_meie_op":
      Reference: "Bits mip.MEIP and mie.MEIE are the interrupt-pending and
interrupt-enable bits for machine-level ext..."
      Current:   "Bits csr:mip[meip] and csr:mie[meie] are the interrupt-pending and
interrupt-enable bits for machine..."
  * "norm:mip_meip_rdonly":
      Reference: "MEIP is read-only in mip, and is set and cleared by a platform-specific
interrupt controller."
      Current:   "csr::[meip] is read-only in csr:mip[], and is set and cleared by a platform-specific
interrupt contr..."
  * "norm:mip_mie_enc_txt":
      Reference: "Interrupt cause number i (as reported in CSR mcause,
<<mcause>>) corresponds with bit i ..."
      Current:   "Interrupt cause number i (as reported in CSR csr:mcause[],
<<mcause>>) corresponds with ..."
  * "norm:mip_mie_std_enc_txt":
      Reference: "The standard portions (bits 15:0) of the mip and mie registers are
formatted as shown in <<nor..."
      Current:   "The standard portions (bits 15:0) of the csr:mip[] and csr:mie[] registers are
formatted as shown in..."
  * "norm:mip_msip_mie_msie_maybe_rdonly0":
      Reference: "If a system has only one hart, or
if a platform standard supports the delivery of machine-level
inte..."
      Current:   "If a system has only one hart, or
if a platform standard supports the delivery of machine-level
inte..."
  * "norm:mip_msip_mie_msie_op":
      Reference: "Bits mip.MSIP and mie.MSIE are the interrupt-pending and
interrupt-enable bits for machine-level sof..."
      Current:   "Bits csr:mip[msip] and csr:mie[msie] are the interrupt-pending and
interrupt-enable bits for machine..."
  * "norm:mip_msip_rdonly":
      Reference: "MSIP is read-only in mip, and is written by accesses to memory-mapped control
registers, which are u..."
      Current:   "csr::[msip] is read-only in csr:mip[], and is written by accesses to memory-mapped control
registers..."
  * "norm:mip_mtip_mie_mtie_op":
      Reference: "Bits mip.MTIP and mie.MTIE are the interrupt-pending and
interrupt-enable bits for machine timer int..."
      Current:   "Bits csr:mip[mtip] and csr:mie[mtie] are the interrupt-pending and
interrupt-enable bits for machine..."
  * "norm:mip_mtip_rdonly":
      Reference: "MTIP is read-only in the mip register, and is cleared by writing to
the memory-mapped machine-mode t..."
      Current:   "csr::[mtip] is read-only in the csr:mip[] register, and is cleared by writing to
the memory-mapped m..."
  * "norm:mip_seip_acc":
      Reference: "SEIP is writable in mip"
      Current:   "csr::[seip] is writable in csr:mip[]"
  * "norm:mip_seip_mie_seie_op":
      Reference: "If supervisor mode is implemented, bits mip.SEIP and mie.SEIE are
the interrupt-pending and interrup..."
      Current:   "If supervisor mode is implemented, bits csr:mip[seip] and csr:mie[seie] are
the interrupt-pending an..."
  * "norm:mip_seip_rdcsr":
      Reference: "When mip is read with a CSR instruction, the value of the
SEIP bit returned in the rd destination re..."
      Current:   "When csr:mip[] is read with a CSR instruction, the value of the
csr::[seip] bit returned in the rd d..."
  * "norm:mip_seip_wrcsr":
      Reference: "the signal from the interrupt controller is not used to
calculate the value written to SEIP. Only th..."
      Current:   "the signal from the interrupt controller is not used to
calculate the value written to csr::[seip]. ..."
  * "norm:mip_ssip_acc":
      Reference: "SSIP is writable in mip"
      Current:   "csr::[ssip] is writable in csr:mip[]"
  * "norm:mip_ssip_mie_ssie_op":
      Reference: "If supervisor mode is implemented, bits mip.SSIP and mie.SSIE are
the interrupt-pending and interrup..."
      Current:   "If supervisor mode is implemented, bits csr:mip[ssip] and csr:mie[ssie] are
the interrupt-pending an..."
  * "norm:mip_stip_mie_stie_op":
      Reference: "If supervisor mode is implemented, its mip.STIP and mie.STIE are
the interrupt-pending and interrupt..."
      Current:   "If supervisor mode is implemented, its csr:mip[stip] and csr:mie[stie] are
the interrupt-pending and..."
  * "norm:mip_stip_no_stimecmp_acc":
      Reference: "If the stimecmp register is not implemented, STIP is writable in
mip"
      Current:   "If the csr:stimecmp[] register is not implemented, csr::[stip] is writable in
csr:mip[]"
  * "norm:mip_stip_stimecmp_acc":
      Reference: "If the stimecmp (supervisor-mode timer compare) register is
implemented, STIP is read-only in mip"
      Current:   "If the csr:stimecmp[] (supervisor-mode timer compare) register is
implemented, csr::[stip] is read-o..."
  * "norm:mip_stip_stimecmp_clr":
      Reference: "This timer interrupt signal is
cleared by writing stimecmp with a value greater than the current tim..."
      Current:   "This timer interrupt signal is
cleared by writing csr:stimecmp[] with a value greater than the curre..."
  * "norm:mip_stip_stimecmp_op2":
      Reference: "reflects the supervisor-level timer
interrupt signal resulting from stimecmp."
      Current:   "reflects the supervisor-level timer
interrupt signal resulting from csr:stimecmp[]."
  * "norm:mip_sxip_mie_sxie_rdonly0":
      Reference: "If supervisor mode is not implemented, bits SEIP, STIP, and SSIP of
mip and SEIE, STIE, and SSIE of ..."
      Current:   "If supervisor mode is not implemented, bits csr::[seip], csr::[stip], and csr::[ssip] of
csr:mip[] a..."
  * "norm:mip_sz_acc":
      Reference: "The mip register is an MXLEN-bit read/write register containing
information on pending interrupts"
      Current:   "The csr:mip[] register is an MXLEN-bit read/write register containing
information on pending interru..."
  * "norm:misa_acc":
      Reference: "The misa CSR is a WARL read-write register"
      Current:   "The csr:misa[] CSR is a WARL read-write register"
  * "norm:misa_extensions_disabling":
      Reference: "When a standard extension is disabled by clearing its bit in misa, the instructions and CSRs defined..."
      Current:   "When a standard extension is disabled by clearing its bit in csr:misa[], the instructions and CSRs d..."
  * "norm:misa_extensions_disabling_def":
      Reference: "With this definition of implemented, disabling an extension by clearing its bit in misa results in t..."
      Current:   "With this definition of implemented, disabling an extension by clearing its bit in csr:misa[] result..."
  * "norm:misa_extensions_enc_tbl":
      Reference: "Bit|Character|Description
===
0|A|Atomic extension¶1|B|B extension¶2|C|Compressed extension¶3|D|Doub..."
      Current:   "Bit|Character|Description
===
0|csr::[a]|Atomic extension¶1|csr::[b]|B extension¶2|csr::[c]|Compress..."
  * "norm:misa_extensions_impl_def":
      Reference: "For a given RISC-V execution environment, an instruction, extension, or other feature of the RISC-V ..."
      Current:   "For a given RISC-V execution environment, an instruction, extension, or other feature of the RISC-V ..."
  * "norm:misa_inc_ialign":
      Reference: "Writing misa may increase IALIGN, e.g., by disabling the
ext:c[] extension. If an instruction that w..."
      Current:   "Writing csr:misa[] may increase IALIGN, e.g., by disabling the
ext:c[] extension. If an instruction ..."
  * "norm:misa_mxl_acc":
      Reference: "The MXL field is read-only."
      Current:   "The csr::[mxl] field is read-only."
  * "norm:misa_mxl_enc":
      Reference: "MXL|XLEN
===
1
2
3|32
64
Reserved
==="
      Current:   "MXL|XLEN
===
1|32¶2|64¶3|Reserved
==="
  * "norm:misa_mxl_op_isa":
      Reference: "The MXL (Machine XLEN) field encodes the native base integer ISA width as
shown in <<norm:misa..."
      Current:   "The csr::[mxl] (Machine XLEN) field encodes the native base integer ISA width as
shown in <<no..."
  * "norm:misa_mxl_op_nz":
      Reference: "If misa is nonzero, the
MXL field indicates the effective XLEN in M-mode, a constant termed MXLEN."
      Current:   "If csr:misa[] is nonzero, the
csr::[mxl] field indicates the effective XLEN in M-mode, a constant te..."
  * "norm:misa_sz":
      Reference: "The misa CSR is MXLEN bits wide."
      Current:   "The csr:misa[] CSR is MXLEN bits wide."
  * "norm:msip_enc":
      Reference: "bits 31--1 read as zero and bit 0 contains the MSIP bit."
      Current:   "bits 31{endash}1 read as zero and bit 0 contains the csr::[msip] bit."
  * "norm:msip_sz_acc":
      Reference: "A hart's memory-mapped msip register is a 32-bit read/write register"
      Current:   "A hart's memory-mapped csr:msip[] register is a 32-bit read/write register"
  * "norm:msip_update_max_time":
      Reference: "When the memory-mapped msip register changes, it is guaranteed to be
reflected in mip.MSIP eventuall..."
      Current:   "When the memory-mapped csr:msip[] register changes, it is guaranteed to be
reflected in csr:mip[msip..."
  * "norm:mstatus_fs_acc1":
      Reference: "If the F extension is implemented, the FS field shall not be read-only zero."
      Current:   "If the ext:f[] extension is implemented, the csr::[fs] field shall not be read-only zero."
  * "norm:mstatus_fs_acc2":
      Reference: "If neither the F extension nor S-mode is implemented, then FS is read-only zero."
      Current:   "If neither the ext:f[] extension nor S-mode is implemented, then csr::[fs] is read-only zero."
  * "norm:mstatus_fs_no_change_dirty":
      Reference: "If an instruction explicitly or implicitly writes a floating-point
register or the fcsr but does not..."
      Current:   "If an instruction explicitly or implicitly writes a floating-point
register or the csr:fcsr[] but do..."
  * "norm:mstatus_fs_no_dirty_track":
      Reference: "dirtiness might not be tracked at all, in which case the valid FS states
are Off and Dirty, and an a..."
      Current:   "dirtiness might not be tracked at all, in which case the valid FS states
are Off and Dirty, and an a..."
  * "norm:mstatus_fs_op":
      Reference: "The FS field encodes the status of the
floating-point unit state, including the floating-point regis..."
      Current:   "The csr::[fs] field encodes the status of the
floating-point unit state, including the floating-poin..."
  * "norm:mstatus_fs_rdonly0_s_no_f":
      Reference: "If S-mode is implemented but the F extension is not, FS
may optionally be read-only zero."
      Current:   "If S-mode is implemented but the ext:f[] extension is not,
csr::[fs] may optionally be read-only zer..."
  * "norm:mstatus_fs_vs_warl":
      Reference: "The FS[1:0] and VS[1:0] WARL fields"
      Current:   "The csr::[fs][1:0] and csr::[vs][1:0] WARL fields"
  * "norm:mstatus_fs_vs_xs_enc":
      Reference: "Status|FS and VS Meaning|XS Meaning
===
0
1
2
3|Off
Initial
Clean
Dirty|All off
None dirty or clean,..."
      Current:   "Status|FS and VS Meaning|XS Meaning
===
0|Off|All off¶1|Initial|None dirty or clean, some on¶2|Clean..."
  * "norm:mstatus_fs_vs_xs_update_indep_priv":
      Reference: "The status fields will
also be updated during execution of instructions, regardless of privilege mod..."
      Current:   "The status fields are
also updated during execution of instructions, regardless of privilege mode."
  * "norm:mstatus_fs_wr":
      Reference: "Changing the setting of FS has no effect on the contents of the
floating-point register state. In pa..."
      Current:   "Changing the setting of csr::[fs] has no effect on the contents of the
floating-point register state..."
  * "norm:mstatus_mbe_op":
      Reference: "MBE controls whether non-instruction-fetch memory accesses made from M-mode (assuming mstatus.MPRV=0..."
      Current:   "csr::[mbe] controls whether non-instruction-fetch memory accesses made from M-mode (assuming csr:mst..."
  * "norm:mstatus_mdt_clr_mnret":
      Reference: "When the Smdbltrp extension is implemented, the MNRET instruction, provided by the Smrnmi extension,..."
      Current:   "When the ext:smdbltrp[] extension is implemented, the insn:mnret[] instruction, provided by the ext:..."
  * "norm:mstatus_mdt_clr_mret_sret":
      Reference: "The MDT bit is set to 0."
      Current:   "The csr::[mdt] bit is set to 0."
  * "norm:mstatus_mdt_not_set_rnmi":
      Reference: "A trap caused by an RNMI does not set the MDT bit."
      Current:   "A trap caused by an RNMI does not set the csr::[mdt] bit."
  * "norm:mstatus_mdt_rst":
      Reference: "Upon reset, the MDT field is set to 1."
      Current:   "Upon reset, the csr::[mdt] field is set to 1."
  * "norm:mstatus_mdt_sz_warl":
      Reference: "The M-mode-disable-trap (MDT) bit is a WARL field introduced by the Smdbltrp extension."
      Current:   "The M-mode-disable-trap (csr::[mdt]) bit is a WARL field introduced by the ext:smdbltrp[] extension."
  * "norm:mstatus_mie_clr_by_mdt":
      Reference: "When the MDT bit is set to 1 by an explicit CSR write,
the MIE (Machine Interrupt Enable) bit is cle..."
      Current:   "When the csr::[mdt] bit is set to 1 by an explicit CSR write,
the csr::[mie] (Machine Interrupt Enab..."
  * "norm:mstatus_mie_clr_by_mdt_rv64":
      Reference: "For RV64, this clearing occurs regardless of the value written, if any, to the MIE bit by the same w..."
      Current:   "For RV64, this clearing occurs regardless of the value written, if any, to the csr::[mie] bit by the..."
  * "norm:mstatus_mie_set_mdt_0":
      Reference: "The MIE bit can only be set to 1 by an
explicit CSR write if the MDT bit is already 0"
      Current:   "The csr::[mie] bit can only be set to 1 by an
explicit CSR write if the csr::[mdt] bit is already 0"
  * "norm:mstatus_mie_sie_op1":
      Reference: "Global interrupt-enable bits, MIE and SIE, are provided for M-mode and
S-mode respectively."
      Current:   "Global interrupt-enable bits, csr::[mie] and csr::[sie], are provided for M-mode and
S-mode respecti..."
  * "norm:mstatus_mpp_sz":
      Reference: "MPP is two bits wide"
      Current:   "csr::[mpp] is two bits wide"
  * "norm:mstatus_mprv_clr_mret_sret_less_priv":
      Reference: "An MRET or SRET instruction that changes the privilege mode to a mode
less privileged than M also se..."
      Current:   "An insn:mret[] or insn:sret[] instruction that changes the privilege mode to a mode
less privileged ..."
  * "norm:mstatus_mprv_inst_xlat_op":
      Reference: "Instruction address-translation and protection are unaffected by the
setting of MPRV."
      Current:   "Instruction address-translation and protection are unaffected by the
setting of csr::[mprv]."
  * "norm:mstatus_mprv_ldst_op":
      Reference: "When MPRV=0, explicit memory accesses
behave as normal, using the translation and
protection mechani..."
      Current:   "When csr::[mprv]=0, explicit memory accesses
behave as normal, using the translation and
protection ..."
  * "norm:mstatus_mprv_rdonly0_no_umode":
      Reference: "MPRV is read-only 0 if U-mode is not supported; otherwise, it must be writable."
      Current:   "csr::[mprv] is read-only 0 if U-mode is not supported; otherwise, it must be writable."
  * "norm:mstatus_mstatush_xbe_warl":
      Reference: "The MBE, SBE, and UBE bits in mstatus and mstatush are WARL fields that
control the endianness of me..."
      Current:   "The csr::[mbe], csr::[sbe], and csr::[ube] bits in csr:mstatus[] and csr:mstatush[] are WARL fields ..."
  * "norm:mstatus_mxr_op":
      Reference: "When MXR=0, only loads from pages marked readable (R=1 in <<sv32pte>>) will succeed.
Whe..."
      Current:   "When csr::[mxr]=0, only loads from pages marked readable (R=1 in <<sv32pte>>) will succe..."
  * "norm:mstatus_mxr_rdonly0_no_smode":
      Reference: "MXR is read-only 0 if S-mode is not supported or if satp.MODE is read-only 0; otherwise, it must be ..."
      Current:   "csr::[mxr] is read-only 0 if S-mode is not supported or if csr:satp[mode] is read-only 0; otherwise,..."
  * "norm:mstatus_mxr_sum_op_acc_fault":
      Reference: "The MXR and SUM mechanisms only affect the interpretation of permissions encoded in page-table entri..."
      Current:   "The csr::[mxr] and csr::[sum] mechanisms only affect the interpretation of permissions encoded in pa..."
  * "norm:mstatus_sbe_change_fence":
      Reference: "Since changing SBE alters the implementation’s interpretation of these
data structures, if any such ..."
      Current:   "Since changing csr::[sbe] alters the implementation’s interpretation of these
data structures, if an..."
  * "norm:mstatus_sbe_implicit":
      Reference: "For implicit accesses to supervisor-level memory management data
structures, such as page tables, en..."
      Current:   "For implicit accesses to supervisor-level memory management data
structures, such as page tables, en..."
  * "norm:mstatus_sbe_op":
      Reference: "If S-mode is not supported, SBE is read-only 0. Otherwise, SBE controls whether explicit load and st..."
      Current:   "If S-mode is not supported, csr::[sbe] is read-only 0. Otherwise, csr::[sbe] controls whether explic..."
  * "norm:mstatus_sbe_rocopy":
      Reference: "If S-mode is supported, an implementation may make SBE be a read-only
copy of MBE."
      Current:   "If S-mode is supported, an implementation may make csr::[sbe] be a read-only
copy of csr::[mbe]."
  * "norm:mstatus_sd_acc":
      Reference: "The SD bit is a read-only bit"
      Current:   "The csr::[sd] bit is a read-only bit"
  * "norm:mstatus_sd_op1":
      Reference: "summarizes whether either the FS, VS,
or XS fields signal the presence of some dirty state that will..."
      Current:   "summarizes whether either the csr::[fs], csr::[vs],
or csr::[xs] fields signal the presence of some ..."
  * "norm:mstatus_sd_rdonly0":
      Reference: "If FS, XS, and VS are all read-only zero, then SD is also always zero."
      Current:   "If csr::[fs], csr::[vs], and csr::[xs] are all read-only zero, then csr::[sd] is also always zero."
  * "norm:mstatus_sie_spie_rdonly0":
      Reference: "MIE and MPIE must be writable.
If supervisor mode is not implemented, then SIE and SPIE are read-onl..."
      Current:   "csr::[mie] and csr::[mpie] must be writable.
If supervisor mode is not implemented, then csr::[sie] ..."
  * "norm:mstatus_spelp_mpelp_op":
      Reference: "The Zicfilp extension adds the SPELP and MPELP fields that hold the previous
ELP, and are updated as..."
      Current:   "The ext:zicfilp[] extension adds the csr::[spelp] and csr::[mpelp] fields that hold the previous
csr..."
  * "norm:mstatus_spp_sz":
      Reference: "SPP is one bit wide."
      Current:   "csr::[spp] is one bit wide."
  * "norm:mstatus_sum_op":
      Reference: "When SUM=0, S-mode memory accesses to pages that are accessible by U-mode
(U=1 in <<sv32pte&gt..."
      Current:   "When csr::[sum]=0, S-mode memory accesses to pages that are accessible by U-mode
(U=1 in <<sv3..."
  * "norm:mstatus_sum_op_mprv_mpp":
      Reference: "while SUM is ordinarily ignored when not
executing in S-mode, it is in effect when MPRV=1 and MPP=S."
      Current:   "while csr::[sum] is ordinarily ignored when not
executing in S-mode, it is in effect when csr::[mprv..."
  * "norm:mstatus_sum_op_no-vm":
      Reference: "SUM has no effect when page-based virtual memory is not in effect."
      Current:   "csr::[sum] has no effect when page-based virtual memory is not in effect."
  * "norm:mstatus_sum_rdonly0":
      Reference: "SUM is read-only 0 if S-mode is not supported or if satp.MODE is read-only 0; otherwise, it must be ..."
      Current:   "csr::[sum] is read-only 0 if S-mode is not supported or if csr:satp[mode] is read-only 0; otherwise,..."
  * "norm:mstatus_sxl_acc_mxlen64":
      Reference: "When MXLEN=64, if S-mode is not supported, then SXL is read-only zero.
Otherwise, it is a WARL field..."
      Current:   "When MXLEN=64, if S-mode is not supported, then csr::[sxl] is read-only zero.
Otherwise, it is a WAR..."
  * "norm:mstatus_sxl_rdonly_mxlen64":
      Reference: "an implementation may make SXL be a read-only field whose
value always ensures that SXLEN=MXLEN."
      Current:   "an implementation may make csr::[sxl] be a read-only field whose
value always ensures that SXLEN=MXL..."
  * "norm:mstatus_sxl_uxl_enc":
      Reference: "The encoding of these fields is the same as the MXL field of misa, shown in <<norm:misa_mxl_en..."
      Current:   "The encoding of these fields is the same as the csr::[mxl] field of csr:misa[], shown in <<nor..."
  * "norm:mstatus_sxl_uxl_sxlen_uxlen_mxlen32":
      Reference: "When MXLEN=32, the SXL and UXL fields do not exist, and SXLEN=32 and UXLEN=32."
      Current:   "When MXLEN=32, the csr::[sxl] and csr::[uxl] fields do not exist, and SXLEN=32 and UXLEN=32."
  * "norm:mstatus_sxl_uxl_warl_op":
      Reference: "For RV64 harts, the SXL and UXL fields are WARL fields that control the
value of XLEN for S-mode and..."
      Current:   "For RV64 harts, the csr::[sxl] and csr::[uxl] fields are WARL fields that control the
value of XLEN ..."
  * "norm:mstatus_sz_acc":
      Reference: "The mstatus register is an MXLEN-bit read/write register formatted as
shown in <<mstatusreg-rv..."
      Current:   "The csr:mstatus[] register is an MXLEN-bit read/write register formatted as
shown in <<mstatus..."
  * "norm:mstatus_tsr_acc":
      Reference: "TSR is read-only 0 when S-mode is not supported;
otherwise, it must be writable."
      Current:   "csr::[tsr] is read-only 0 when S-mode is not supported;
otherwise, it must be writable."
  * "norm:mstatus_tsr_op":
      Reference: "When TSR=1, attempts to
execute SRET while executing in S-mode will raise an illegal-instruction
exc..."
      Current:   "When csr::[tsr]=1, attempts to
execute insn:sret[] while executing in S-mode will raise an illegal-i..."
  * "norm:mstatus_tsr_warl":
      Reference: "The TSR (Trap SRET) bit is a WARL field that supports intercepting the
supervisor exception return i..."
      Current:   "The csr::[tsr] (Trap insn:sret[]) bit is a WARL field that supports intercepting the
supervisor exce..."
  * "norm:mstatus_tvm_warl_op":
      Reference: "The TVM (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtual-memo..."
      Current:   "The csr::[tvm] (Trap Virtual Memory) bit is a WARL field that supports intercepting supervisor virtu..."
  * "norm:mstatus_tw_acc":
      Reference: "TW is read-only 0 when there are no modes less privileged than M;
otherwise, it must be writable."
      Current:   "csr::[tw] is read-only 0 when there are no modes less privileged than M;
otherwise, it must be writa..."
  * "norm:mstatus_tw_always_illegal":
      Reference: "An implementation may have WFI always
raise an illegal-instruction exception in modes less privilege..."
      Current:   "An implementation may have insn:wfi[] always
raise an illegal-instruction exception in modes less pr..."
  * "norm:mstatus_tw_op":
      Reference: "When TW=0, the WFI
instruction may execute in modes less privileged than M when not prevented for
so..."
      Current:   "When csr::[tw]=0, the insn:wfi[] instruction may execute in modes less privileged than M when not pr..."
  * "norm:mstatus_tw_umode_op":
      Reference: "When S-mode is implemented, then executing WFI in U-mode causes an
illegal-instruction exception, re..."
      Current:   "When S-mode is implemented, then executing insn:wfi[] in U-mode causes an
illegal-instruction except..."
  * "norm:mstatus_tw_warl":
      Reference: "The TW (Timeout Wait) bit is a WARL field that supports intercepting the WFI
instruction (see <&l..."
      Current:   "The csr::[tw] (Timeout Wait) bit is a WARL field that supports intercepting the
insn:wfi[] instructi..."
  * "norm:mstatus_ube_op":
      Reference: "If U-mode is not supported, UBE is read-only 0. Otherwise, UBE controls whether explicit load and st..."
      Current:   "If U-mode is not supported, csr::[ube] is read-only 0. Otherwise, UBE controls whether explicit load..."
  * "norm:mstatus_ube_rocopy":
      Reference: "If U-mode is supported, an implementation may make UBE be a
read-only copy of either MBE or SBE."
      Current:   "If U-mode is supported, an implementation may make csr::[ube] be a
read-only copy of either csr::[mb..."
  * "norm:mstatus_uxl_acc_mxlen64":
      Reference: "When MXLEN=64, if U-mode is not supported, then UXL is read-only zero.
Otherwise, it is a WARL field..."
      Current:   "When MXLEN=64, if U-mode is not supported, then csr::[uxl] is read-only zero.
Otherwise, it is a WAR..."
  * "norm:mstatus_uxl_legal_vals_smode":
      Reference: "If S-mode is implemented, the set of legal values that the UXL field may assume excludes those that ..."
      Current:   "If S-mode is implemented, the set of legal values that the csr::[uxl] field may assume excludes thos..."
  * "norm:mstatus_uxl_rdonly_mxlen64":
      Reference: "an implementation may make UXL be a read-only field whose
value always ensures that UXLEN=MXLEN or U..."
      Current:   "an implementation may make csr::[uxl] be a read-only field whose
value always ensures that UXLEN=MXL..."
  * "norm:mstatus_vs_acc1":
      Reference: "If the v registers are implemented, the VS field shall not be read-only zero."
      Current:   "If the v registers are implemented, the csr::[vs] field shall not be read-only zero."
  * "norm:mstatus_vs_acc2":
      Reference: "If neither the v registers nor S-mode is implemented, then VS is
read-only zero."
      Current:   "If neither the v registers nor S-mode is implemented, then csr::[vs] is
read-only zero."
  * "norm:mstatus_vs_imprecise":
      Reference: "Implementations may choose to track the dirtiness of the vector register
state in an analogous impre..."
      Current:   "Implementations may choose to track the dirtiness of the vector register
state in an analogous impre..."
  * "norm:mstatus_vs_no_change_dirty":
      Reference: "When VS=Initial or VS=Clean, it is implementation-defined whether an
instruction that writes a vecto..."
      Current:   "When csr::[vs]=Initial or csr::[vs]=Clean, it is implementation-defined whether an
instruction that ..."
  * "norm:mstatus_vs_op":
      Reference: "The VS field encodes the status of the
vector extension state, including the vector
registers v0–v31..."
      Current:   "The csr::[vs] field encodes the status of the
vector extension state, including the vector
registers..."
  * "norm:mstatus_vs_rdonly0_s_no_v":
      Reference: "If S-mode is implemented but the v registers are not,
VS may optionally be read-only zero."
      Current:   "If S-mode is implemented but the v registers are not,
csr::[vs] may optionally be read-only zero."
  * "norm:mstatus_xret_op":
      Reference: "When executing an xRET instruction, supposing
xPP holds the value y, xIE is set to xPIE; the privile..."
      Current:   "When executing an xRET instruction, supposing
xPP holds the value y, xIE is set to xPIE; the privile..."
  * "norm:mstatus_xs_acc":
      Reference: "In harts without additional user extensions requiring new state, the
XS field is read-only zero."
      Current:   "In harts without additional user extensions requiring new state, the
csr::[xs] field is read-only ze..."
  * "norm:mstatus_xs_equiv":
      Reference: "Every additional extension with state
provides a CSR field that encodes the equivalent of the XS sta..."
      Current:   "Every additional extension with state
provides a CSR field that encodes the equivalent of the csr::[..."
  * "norm:mstatus_xs_op1":
      Reference: "The XS field encodes the status of
additional user-mode extensions and associated state."
      Current:   "The csr::[xs] field encodes the status of
additional user-mode extensions and associated state."
  * "norm:mstatus_xs_op2":
      Reference: "The XS field represents a summary of all extensions' status as shown in
<<norm:mstatus_fs_vs_x..."
      Current:   "The csr::[xs] field represents a summary of all extensions' status as shown in
<<norm:mstatus_..."
  * "norm:mstatush_enc":
      Reference: "Bits 30:4 of mstatush generally contain the same fields found in bits 62:36 of mstatus for RV64. Fie..."
      Current:   "Bits 30:4 of csr:mstatush[] generally contain the same fields found in bits 62:36 of csr:mstatus[] f..."
  * "norm:mstatush_sz_acc":
      Reference: "For RV32 only, mstatush is a 32-bit read/write register formatted as shown in <<mstatushreg&gt..."
      Current:   "For RV32 only, csr:mstatush[] is a 32-bit read/write register formatted as shown in <<mstatush..."
  * "norm:mtvec_base_align_4B":
      Reference: "The value in the BASE field must
always be aligned on a 4-byte boundary"
      Current:   "The value in the csr::[base] field must
always be aligned on a 4-byte boundary"
  * "norm:mtvec_base_align_func_mode":
      Reference: "the MODE setting may impose
additional alignment constraints on the value in the BASE field."
      Current:   "the csr::[mode] setting may impose
additional alignment constraints on the value in the csr::[base] ..."
  * "norm:mtvec_mandatory":
      Reference: "The mtvec register must always be implemented"
      Current:   "The csr:mtvec[] register must always be implemented"
  * "norm:mtvec_mode_direct_op":
      Reference: "When MODE=Direct, all traps into
machine mode cause the pc to be set to the address in the BASE fiel..."
      Current:   "When csr::[mode]=Direct, all traps into
machine mode cause the pc to be set to the address in the cs..."
  * "norm:mtvec_mode_enc":
      Reference: "Value|Name|Description
===
0|Direct|All traps set pc to BASE.¶1|Vectored|Asynchronous interrupts set..."
      Current:   "Value|Name|Description
===
0|Direct|All traps set pc to csr::[base].¶1|Vectored|Asynchronous interru..."
  * "norm:mtvec_mode_vectored_op":
      Reference: "When MODE=Vectored, all synchronous exceptions into machine mode cause
the pc to be set to the addre..."
      Current:   "When csr::[mode]=Vectored, all synchronous exceptions into machine mode cause
the pc to be set to th..."
  * "norm:mtvec_sz_warl_acc":
      Reference: "The mtvec register is an MXLEN-bit WARL read/write register that holds
trap vector configuration, co..."
      Current:   "The csr:mtvec[] register is an MXLEN-bit WARL read/write register that holds
trap vector configurati..."
  * "norm:mvendorid_sz_acc_op":
      Reference: "The mvendorid CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the provider..."
      Current:   "The csr:mvendorid[] CSR is a 32-bit read-only register providing the JEDEC
manufacturer ID of the pr..."
  * "norm:pm_uxl_clear":
      Reference: "Setting UXL/SXL/MXL to 1 will clear the corresponding pointer masking configuration bits."
      Current:   "Setting UXL/SXL to 1 will clear the corresponding pointer masking configuration bits."
  * "norm:sstatus_sdt_clr_mnret":
      Reference: "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then ssta..."
      Current:   "If the ext:ssdbltrp[] extension is also implemented, and the new privilege mode is U, VS, or VU, the..."
  * "norm:sstatus_sdt_clr_mret_sret":
      Reference: "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then ssta..."
      Current:   "If the Ssdbltrp extension is also implemented, and the new privilege mode is U, VS, or VU, then csr:..."
  * "norm:trap_del_S_mode_no_M_mode":
      Reference: "The mcause, mepc, and mtval registers and the MPP and MPIE fields of
mstatus are not written."
      Current:   "The csr:mcause[], csr:mepc[], and csr:mtval[] registers and the csr::[mpp] and csr::[mpie] fields of..."
  * "norm:trap_del_S_mode_op":
      Reference: "the scause register is written
with the trap cause; the sepc register is written with the virtual
ad..."
      Current:   "the csr:scause[] register is written
with the trap cause; the csr:sepc[] register is written with th..."
  * "norm:trap_del_intr_priv_lvl":
      Reference: "Delegated interrupts result in the interrupt being masked at the
delegator privilege level. For exam..."
      Current:   "Delegated interrupts result in the interrupt being masked at the
delegator privilege level. For exam..."
  * "norm:trap_exp":
      Reference: "When a trap is to be taken into M-mode, if the MDT bit is currently 0, it is then set to 1, and the ..."
      Current:   "When a trap is to be taken into M-mode, if the csr::[mdt] bit is currently 0, it is then set to 1, a..."
  * "norm:trap_unexp_hndl_no_rnmi":
      Reference: "When the Smrnmi extension is not implemented, or if the Smrnmi extension is
implemented and mnstatus..."
      Current:   "When the ext:smrnmi[] extension is not implemented, or if the ext:smrnmi[] extension is
implemented ..."
  * "norm:trap_unexp_hndl_rnmi":
      Reference: "When the Smrnmi extension is implemented and mnstatus.NMIE is 1, the hart
traps to the RNMI handler...."
      Current:   "When the Smrnmi extension is implemented and csr:mnstatus[nmie] is 1, the hart
traps to the RNMI han..."
  * "norm:trap_unexp_mdt_1":
      Reference: "However, if MDT is already set to 1, then this is an unexpected trap."
      Current:   "However, if csr::[mdt] is already set to 1, then this is an unexpected trap."
  * "norm:trap_unexp_mnstatus_nmie_0":
      Reference: "a trap that occurs when executing in M-mode with
mnstatus.NMIE set to 0 is an unexpected trap."
      Current:   "a trap that occurs when executing in M-mode with
csr:mnstatus[nmie] set to 0 is an unexpected trap."
  * "norm:trap_unexp_rnmi":
      Reference: "When the Smrnmi extension
is implemented, a trap caused by an RNMI is not considered an unexpected t..."
      Current:   "When the ext:smrnmi[] extension
is implemented, a trap caused by an RNMI is not considered an unexpe..."
  * "norm:vsstatus_sdt_clr_mnret":
      Reference: "Additionally, if it is VU, then vsstatus.SDT is also set to 0."
      Current:   "Additionally, if it is VU, then csr:vsstatus[sdt] is also set to 0."
  * "norm:vsstatus_sdt_clr_mret_sret":
      Reference: "Additionally, if it is VU, then vsstatus.SDT is also set to 0."
      Current:   "Additionally, if it is VU, then csr:vsstatus[sdt] is also set to 0."
  * "norm:xlen_reduction_hint_op1":
      Reference: "Some HINT instructions are encoded as integer computational instructions that overwrite their destin..."
      Current:   "Some HINT instructions are encoded as integer computational instructions that overwrite their destin..."
  * "norm:zicflip_elp_lpad_expected":
      Reference: "When ELP is set to LP_EXPECTED, if the next instruction in the instruction stream is not 4-byte alig..."
      Current:   "When csr::[elp] is set to LP_EXPECTED, if the next instruction in the instruction stream is not 4-by..."
  * "norm:zicflip_indirect_branch_lpad":
      Reference: "An indirect branch using insn:jalr[], insn:c.jalr[], or insn:c.jr[] with rs1 as x7 is termed a softw..."
      Current:   "An indirect branch using insn:jalr[], insn:c.jalr[], or insn:c.jr[] with rs1 as x7 is termed a softw..."
  * "norm:zicflip_lpad_alignment_exception":
      Reference: "The pc is not 4-byte aligned and ELP is LP_EXPECTED."
      Current:   "The pc is not 4-byte aligned and csr::[elp] is LP_EXPECTED."
  * "norm:zicflip_lpad_enabled_instr_allowed":
      Reference: "When ext:zicfilp[] is enabled, insn:lpad[] is the only instruction allowed to execute when
the ELP s..."
      Current:   "When ext:zicfilp[] is enabled, insn:lpad[] is the only instruction allowed to execute when
the csr::..."
  * "norm:zicflip_lpad_expected":
      Reference: "The ext:zicfilp[] extension, when enabled, determines if an indirect call or an indirect jump must l..."
      Current:   "The ext:zicfilp[] extension, when enabled, determines if an indirect call or an indirect jump must l..."
  * "norm:zicflip_lpad_label_exception":
      Reference: "The ELP is LP_EXPECTED and the LPL is not zero and the LPL does not match the expected landing pad l..."
      Current:   "The csr::[elp] is LP_EXPECTED and the LPL is not zero and the LPL does not match the expected landin..."
  * "norm:zicflip_lpad_no_sw_exception":
      Reference: "If a software-check exception is not caused then the ELP is updated to NO_LP_EXPECTED."
      Current:   "If a software-check exception is not caused then the csr::[elp] is updated to NO_LP_EXPECTED."

================================================================================
Summary: 175 total changes
  Added:    0
  Deleted:  2
  Modified: 173
================================================================================

---

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