Release riscv-isa-release-bebacf2-2025-12-09

This release was created by: aswaterman
Release of RISC-V ISA, built from commit bebacf2, is now available.

What's Changed

• Remove remark about implementing wide coutners with traps by @aswaterman in #2473
• Mention IALIGN in NOTEs on misaligned fetch exceptions by @aswaterman in #2474
• Improve R-type ALU op section title by @aswaterman in #2475
• Bump softprops/action-gh-release from 2.4.2 to 2.5.0 by @dependabot[bot] in #2450
• Hyphenate "right-shift type" by @aswaterman in #2478
• "Loads and stores" -> "Explicit memory accesses" by @aswaterman in #2479
• Update PMP spec to use "memory operation" by @Timmmm in #1434
• Clarify that misaligned atomicity granule PMA applies to the compress… by @romanheros in #1557
• Define format of memory-mapped msip register by @aswaterman in #1541
• Fix backticks in HTML by @pfusik in #2434
• Update .PHONY rules in Makefile by @Timmmm in #2375
• Update CTR chapter with NT branch target info, addresses issue #2349 by @bcstrongx in #2361

New Contributors

• @romanheros made their first contribution in #1557

Full Changelog: riscv-isa-release-5c6e7d7-2025-12-09...riscv-isa-release-bebacf2-2025-12-09