ROM-less CORDIC engine for Tiny Tapeout

This ROM-less cordic engine is written for Tiny Tapeout SKY25a shuttle. It implements a COordinate Rotation Digital Computer or CORDIC which work on a 16-bit signed fixed-point input Q3.16 (1 sign bit, 3 integer bits, and 12 fraction bits). This engine utilizes SPI-slave interface to receive four 16-bit signed fixed-point inputs (atan₀, alpha, x, y) and returns three 16-bit signed fixed-point outputs (alpha, cosθ, sinθ).

• Read the documentation for project
• Try this verilog design on FPGA
• Check 3D render of silicon here

Specification

• Tile area: 334.88um x 225.76um
• Stdcell count: 4042 total cells (excluding fill and tap cells)
• Routing utilization : 41.216 %
• Max Clk freq supported by design: 50 MHz
• No. of inputs: 3
  • SCLK
  • MOSI
  • CS_N
• No. of outputs: 2
  • MISO
  • INTERRUPT

2D render for the ROM-less CORDIC Engine

Our Team

Rohan Sundar, Rohan Verma and Jyotinder Singh

While building the foundation for math processors on ASIC, we learnt a lot.

Vicharak Team engineered a good synthesizable RTL that has been thoroughly tested and integrates beautifully with open-source tools.

Rohan Sundar and Kasetty Praveen Kumar were instrumental in simplifying the CORDIC engine’s math to enable a ROM-less design. A special mention to Rishik Ram Jallarapu for his dedicated contributions in verification, GDS generation, and gate-level simulations.

Vicharak's Engineering Team

Devang Kabutarwala, Kasetty Praveen Kumar, Rishik Ram Jallarapu, Deepak Sharda, Tejas Dabhankar, Akshar Vastarpara

🙏 Acknowledgment

Huge thanks to Vicharak's Engineering Team 🏆 for their expertise in mathematics, RTL design, and testbench simulations.

Thanks to Matthew Venn, Uri Shaked and whole Tiny Tapeout team for answering our queries related to ASIC.

This tapeout simply wouldn’t have been possible without their hard work and support.