Add Xilinx Zynq-A9 example.#202
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This looks fantastic - just a couple of minor notes (and I've made a PR to fix the redundant Because we already test single-core Armv7-A on the Versatile board, I'd be happy to see this example later modified to do SMP bring-up (and not have a single core variant). The only reason the MPS3-AN536 has both single-core and dual-core versions is because there isn't anything that would otherwise test ARMv8-R in single-core mode, and dual-core mode currently involves bypassing a bunch of the aarch32-rt start-up code that we want to test. |
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@jonathanpallant Thank you for the review. I've updated the patch accordingly, please have a look. And, yes I'm working on the SMP patch hoping to have it by this week. |
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You should still test thumbv7a-none-eabi and -eabihf, but like ./tests.sh examples/xilinx-zynq-a9 thumbv7a-none-eabi {{verbose}} --release || FAIL=1 |
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@ me when this is ready for review again (I didn't understand your last force-push, btw...) |
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@jonathanpallant Done, the force push was I added a linebreak which was not needed. Added the test to justfile. Updated. Please have a look. |
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Yeah but the force push removed a line break so a cfg attribute ended up attached to a comment, which made no sense. The build also failed because of random spacing in the just file, which would have been extremely obvious if you had run the build locally before pushing. I've attempted to propose fixes, but I was on my phone so I might have made some typos. |
The example follows the versatileab layout: * `memory.x` : 128 MiB of DDR at 0x00, matching QEMU's default RAM region * `src/mmu.rs` : L1 page table mapping DDR as normal cacheable memory. * `src/bin/hello.rs`: semihosting hello-world This patch is a preparatory work for the SMP based Xilin Zynq A9 which needs further components like the Gic, timers to be introduced. Please refer to README.md for running instructions and references for the golden standard outputs Signed-off-by: Sriram Raghunathan <sriram@hcoop.net>
* Disable Zbuild_core prioritizing rustup toolchain offerings. * Disable cfg feature as the build is specific for "v7-a". * Remove the cfg feature to build v7-r Signed-off-by: Sriram Raghunathan <sriram@hcoop.net>
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The example follows the versatileab layout:
memory.x: 128 MiB of DDR at 0x00, matching QEMU's default RAM regionsrc/mmu.rs: L1 page table mapping DDR as normal cacheable memory.src/bin/hello.rs: semihosting hello-worldThis patch is a preparatory work for the SMP based Xilin Zynq A9 which needs further components like the Gic, timers to be introduced.
Please refer to README.md for running instructions and references for the golden standard outputs