- Baveria, Germany
- in/shobhit-mittra
Pinned Loading
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baseband_processor
baseband_processor PublicDesign of a simple base-band processor using Verilog HDL and hardwaree implementation of Spartan-7 fpga unit, as a part of the HDL Chip Design Laboratory at TUM
Verilog
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low-power-adiabatic-design-D-FlipFlop
low-power-adiabatic-design-D-FlipFlop PublicThis project is a part of the report for my 7th semester program elective (EC-4152 Low Power VLSI Design).
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tcl_box
tcl_box PublicThis repository is dedicated to learning and improving my TCL scripting and related concepts. This project is inspired by the Udemy course by Kunal Gosh sir titled : 'VSD - TCL programming from nov…
Tcl
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Tcl_parser
Tcl_parser PublicThis repository is my entry into scripting using TCL and an attempt to understand it's nuances in physical design flow in VLSI
Tcl 1
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vsd_pd_workshop
vsd_pd_workshop PublicThis repository serves as an archive of all the knowledge I acquired and encountered during the VSD-Advanced Physical Design workshop. I have utilised several snippets to demonstrate the ideas I ga…
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