uart: half stopbit support, speedup and bit boundaries refinement

[sespivak]

1. Reduced amount of IDLE events by doubling of IDLE period of each frame since 3rd. Max IDLE period equals samplerate, thus IDLE events min frequency is 1 Hz. This approach decreases function calls up to 10 times at idle periods, depends on data sparsity and baudrate selected.
2. Start and end of signal boundaries refined. There is no overlap in data bits annotations now. Also packets boundaries are frame boundaries, because packet transmission actually starts at start bit and ends with stop bit.
3. Calculations of constants in start() to avoid unnecessary overhead at runtime.
4. New option put_sample_points added to put sample points at dedicated annotation rows with corresponding signal values.
5. Half stopbit values support (0.5 and 1.5)
6. A state machine to control the whole decode process. It also contains precomputed sample point values and exact sample values for the current bit boundaries.
7. Interrupt receiving stop bits on stop bit error and put stopbit error in annotation
8. Put data packets to python output
9. Put actual and expected signal at parity error to python output instead of dummy tuple
10. Raise an exception BaudrateError if baudrate option value is not positive
11. Testcases updated to match new bits/data boundaries. sigrok-test #18

Speed measurements were made using a set of tests:

time ../sigrok-test/decoder/pdtest -r modbus lin amulet_ascii uart midi

Average time without patches on my pc (i5-4250U):
real 2m47s
Average time with patch:
real 1m29s

So the speedup is around 88%. If the dataset is sparse, the speedup is even greater, up to 400%.

This patch based on PR #90 and contains 2 commits - 1 old from #90 and 1 new, described here.