How many cycles does PIO code takes in logic_analyzer?

[pc2005cz]

Hi,

Is this comment correct?

hsdaoh-rp2350/apps/logic_analyzer/logic_analyzer.c

Lines 46 to 47 in e4d3619

	/* The PIO is running with sys_clk, and needs 10 cycles per sample,
	* so the LA is sampling with 32 MHz */

When I wrote a replacement PIO code for decreased pin count (so I can send samples more often) the buffer had always overflown.

When I looked back into the original PIO code

hsdaoh-rp2350/apps/logic_analyzer/16bit_input.pio

Lines 14 to 26 in e4d3619

	.wrap_target
	; GP0 - GP11 are contiguous, then come the HSTX pins which are already in use
	; Next pins we can use are 20, 21, 22 and then 26, 27, 28
	mov osr, pins ; Sample all 32 pins
	in osr, 12 ; shift values of GP0-GP11 to ISR
	out null, 20 ; shift out GP0-GP11 and discard GP12-GP19
	in osr, 3 ; shift in GP20 - GP22
	out null, 6 ; drop GP20 - GP25
	in osr, 1 ; shift in GP26 - now the ISR is full and the autopush is happening
	in null, 16 ; fill with zeroes so that data is in lower 16 bits
	nop [3]
	.wrap

it seems it actually takes 11 cycles to run (nop [3] is 1+3)? I don't have a much experience with PIO system. Can you confirm the logic_analyzer is designed for 11 cycles per sample?

[steve-m]

Yes, that indeed is a bug... it should be nop [2] and then instead use a little bit higher HSTX clock so there is enough bandwidth.

I also got 275 MByte/s working with MS2130S, haven't really gotten around to clean up and push it though... That would allow quite a bit higher LA speeds with the pico2.