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🐛 fix bug in Zalrsc ISA extension #1190

Merged
merged 3 commits into from
Feb 20, 2025
Merged

🐛 fix bug in Zalrsc ISA extension #1190

merged 3 commits into from
Feb 20, 2025

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stnolting
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Some normal memory operations were treated as LR.W / SC.W instructions. This PR fixes the incomplete bus type decoding.

As a minor edit, this PR also disables all optional CPU extensions by default (primarily Zicntr).

@stnolting stnolting added bug Something isn't working as expected HW Hardware-related labels Feb 20, 2025
@stnolting stnolting self-assigned this Feb 20, 2025
@stnolting stnolting marked this pull request as ready for review February 20, 2025 22:08
@stnolting stnolting merged commit ddc863b into main Feb 20, 2025
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@stnolting stnolting deleted the lrsc_fix branch February 20, 2025 22:32
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