stnolting · stnolting · Feb 1, 2026 · Jan 31, 2026 · Jan 31, 2026 · Jan 31, 2026
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
 
 | Date | Version | Comment | Ticket |
 |:----:|:-------:|:--------|:------:|
+| 31.01.2025 | 1.12.7.6 | :warning: rename `Zxcfu` ISA extension to `Xcfu` | [#1487](https://github.com/stnolting/neorv32/pull/1487) |
 | 30.01.2025 | 1.12.7.5 | :bug: fix enabling of `Zbkx` ISA extension | [#1486](https://github.com/stnolting/neorv32/pull/1486) |
 | 22.01.2025 | 1.12.7.4 | :warning: rework memory image files | [#1482](https://github.com/stnolting/neorv32/pull/1482) |
 | 18.01.2025 | 1.12.7.3 | :sparkles: encapsulate memory components; caches: use block invalidation when a bus error occurs during block download | [#1481](https://github.com/stnolting/neorv32/pull/1481) |

diff --git a/README.md b/README.md
@@ -109,15 +109,15 @@ setup according to your needs. Note that all of the following SoC modules are en
 [`Zksed`](https://stnolting.github.io/neorv32/#_zksed_isa_extension)
 [`Zksh`](https://stnolting.github.io/neorv32/#_zksh_isa_extension)
 [`Zmmul`](https://stnolting.github.io/neorv32/#_zmmul_isa_extension)
-[`Zxcfu`](https://stnolting.github.io/neorv32/#_zxcfu_isa_extension)
 [`Sdext`](https://stnolting.github.io/neorv32/#_sdext_isa_extension)
 [`Sdtrig`](https://stnolting.github.io/neorv32/#_sdtrig_isa_extension)
 [`Smcntrpmf`](https://stnolting.github.io/neorv32/#_smcntrpmf_isa_extension)
 [`Smpmp`](https://stnolting.github.io/neorv32/#_smpmp_isa_extension)
+[`Xcfu`](https://stnolting.github.io/neorv32/#_xcfu_isa_extension)
 * compatible to subsets of the RISC-V "Unprivileged ISA Specification" and "Privileged Architecture Specification"
 * `machine` and `user` privilege modes
 * implements **all** standard RISC-V exceptions and interrupts + 16 fast interrupt request channels as NEORV32-specific extension
-* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu) as `Zxcfu` ISA extension)
+* custom functions unit ([CFU](https://stnolting.github.io/neorv32/#_custom_functions_unit_cfu) as custom `Xcfu` ISA extension)
 for **custom RISC-V instructions**
 
 **Memories**

diff --git a/docs/datasheet/cpu_cfu.adoc b/docs/datasheet/cpu_cfu.adoc
@@ -2,7 +2,7 @@
 :sectnums:
 === Custom Functions Unit (CFU)
 
-The Custom Functions Unit (CFU) is the central part of the NEORV32-specific <<_zxcfu_isa_extension>> and
+The Custom Functions Unit (CFU) is the central part of the custom NEORV32-specific <<_xcfu_isa_extension>> and
 represents the actual hardware module that can be used to implement **custom RISC-V instructions**.
 These are intended for operations that are inefficient in terms of performance, latency, energy consumption or
 program memory requirements when implemented entirely in software.

diff --git a/docs/datasheet/cpu_csr.adoc b/docs/datasheet/cpu_csr.adoc
@@ -1010,7 +1010,7 @@ discover additional ISA (sub-)extensions and CPU configuration options.
 |  0  | `CSR_MXISA_ZICSR`     | r/- | <<_zicsr_isa_extension>> available
 |  1  | `CSR_MXISA_ZIFENCEI`  | r/- | <<_zifencei_isa_extension>> available
 |  2  | `CSR_MXISA_ZMMUL`     | r/- | <<_zmmul_isa_extension>> available
-|  3  | `CSR_MXISA_ZXCFU`     | r/- | <<_zxcfu_isa_extension>> available
+|  3  | `CSR_MXISA_XCFU`      | r/- | <<_xcfu_isa_extension>> available
 |  4  | `CSR_MXISA_ZKT`       | r/- | <<_zkt_isa_extension>> available
 |  5  | `CSR_MXISA_ZFINX`     | r/- | <<_zfinx_isa_extension>> available
 |  6  | `CSR_MXISA_ZICOND`    | r/- | <<_zicond_isa_extension>> available

diff --git a/docs/datasheet/cpu_isa.adoc b/docs/datasheet/cpu_isa.adoc
@@ -45,11 +45,11 @@ This chapter gives a brief overview of all available ISA extensions.
 | <<_zksh_isa_extension,`Zksh`>>           | Scalar cryptography ShangMi hash instructions                | <<_processor_top_entity_generics, `RISCV_ISA_Zksh`>>
 | <<_zkt_isa_extension,`Zkt`>>             | Data independent execution time (of cryptography operations) | _Implicitly_ enabled
 | <<_zmmul_isa_extension,`Zmmul`>>         | Integer multiplication-only instructions (subset of `M`)     | <<_processor_top_entity_generics, `RISCV_ISA_Zmmul`>>
-| <<_zxcfu_isa_extension,`Zxcfu`>>         | Custom / user-defined instructions                           | <<_processor_top_entity_generics, `RISCV_ISA_Zxcfu`>>
 | <<_sdext_isa_extension,`Sdext`>>         | External debug support extension (on-chip debugger)          | <<_processor_top_entity_generics, `OCD_EN`>>
 | <<_sdtrig_isa_extension,`Sdtrig`>>       | Debug trigger module extension (hardware breakpoint)         | <<_processor_top_entity_generics, `OCD_NUM_HW_TRIGGERS`>>
 | <<_smcntrpmf_isa_extension,`Smcntrpmf`>> | Counter privilege-mode filtering                             | <<_processor_top_entity_generics, `RISCV_ISA_Smcntrpmf`>>
 | <<_smpmp_isa_extension,`Smpmp`>>         | Physical memory protection (PMP) extension                   | <<_processor_top_entity_generics, `RISCV_ISA_Smpmp`>>
+| <<_xcfu_isa_extension,`Xcfu`>>           | Custom / user-defined instructions                           | <<_processor_top_entity_generics, `RISCV_ISA_Xcfu`>>
 |=======================
 
 .RISC-V ISA Specification
@@ -703,9 +703,9 @@ of the `M` extensions and is intended for size-constrained setups that require h
 integer multiplications but not hardware-based divisions, which will be computed entirely in software.
 
 
-==== `Zxcfu` ISA Extension
+==== `Xcfu` ISA Extension
 
-The `Zxcfu` presents a NEORV32-specific ISA extension. It adds the <<_custom_functions_unit_cfu>> to
+The `Xcfu` presents a custom NEORV32-specific ISA extension. It adds the <<_custom_functions_unit_cfu>> to
 the CPU core, which allows to add custom RISC-V instructions to the processor core.
 For detailed information regarding the CFU, its hardware and the according software interface
 see section <<_custom_functions_unit_cfu>>.

diff --git a/docs/datasheet/overview.adoc b/docs/datasheet/overview.adoc
@@ -186,7 +186,7 @@ rtl/core
 ├─ neorv32_cpu_control.vhd       - CPU control, exception system and CSRs
 ├─ neorv32_cpu_counters.vhd      - Hardware counters (Zicntr & Zihpm ext.)
 ├─ neorv32_cpu_alu_bitmanip.vhd  - Bit-manipulation unit (B ext.)
-├─ neorv32_cpu_alu_cfu.vhd       - Custom instructions unit (Zxcfu ext.)
+├─ neorv32_cpu_alu_cfu.vhd       - Custom instructions unit (Xcfu ext.)
 ├─ neorv32_cpu_alu_cond.vhd      - Integer conditional unit (Zicond ext.)
 ├─ neorv32_cpu_alu_crypto.vhd    - Scalar cryptography unit (Zk*/Zbk* ext.)
 ├─ neorv32_cpu_alu_fpu.vhd       - Floating-point unit (Zfinx ext.)

diff --git a/docs/datasheet/soc.adoc b/docs/datasheet/soc.adoc
@@ -243,8 +243,8 @@ The generic type "`suv(x:y)`" is an abbreviation for "`std_ulogic_vector(x downt
 | `RISCV_ISA_Zksed`       | boolean   | false         | Enable <<_zksed_isa_extension>> (scalar cryptography ShangMi block cyphers).
 | `RISCV_ISA_Zksh`        | boolean   | false         | Enable <<_zksh_isa_extension>> (scalar cryptography ShangMi hash functions).
 | `RISCV_ISA_Zmmul`       | boolean   | false         | Enable <<_zmmul_isa_extension>> (hardware-based integer multiplication).
-| `RISCV_ISA_Zxcfu`       | boolean   | false         | Enable NEORV32-specific <<_zxcfu_isa_extension>> (custom RISC-V instructions).
 | `RISCV_ISA_Smcntrpmf`   | boolean   | false         | Enable <<_smcntrpmf_isa_extension>> (counter privilege-mode filtering).
+| `RISCV_ISA_Xcfu`        | boolean   | false         | Enable NEORV32-specific <<_xcfu_isa_extension>> (custom RISC-V instructions).
 4+^| **<<_cpu_tuning_options>>**
 | `CPU_CONSTT_BR_EN`      | boolean   | false         | Implement constant-time branches (same execution times for taken and not-taken branches).
 | `CPU_FAST_MUL_EN`       | boolean   | false         | Implement fast but large full-parallel multipliers (trying to infer DSP blocks); see section <<_cpu_arithmetic_logic_unit>>.

diff --git a/docs/datasheet/soc_cfs.adoc b/docs/datasheet/soc_cfs.adoc
@@ -39,7 +39,7 @@ real-time data transport (I2S) or just replication of existent NEORV32 periphera
 .Custom ISA Instructions
 [TIP]
 If you like to implement _custom instructions_ that are executed right within the CPU's ALU
-see the <<_zxcfu_isa_extension>> and the according <<_custom_functions_unit_cfu>>.
+see the <<_xcfu_isa_extension>> and the according <<_custom_functions_unit_cfu>>.
 
 .CFS Template
 [TIP]

diff --git a/docs/figures/neorv32_processor.png b/docs/figures/neorv32_processor.png
diff --git a/docs/userguide/simulating_the_processor.adoc b/docs/userguide/simulating_the_processor.adoc
@@ -129,7 +129,7 @@ GHDL simulation run parameters: --stop-time=10ms <4>
 ../rtl/core/neorv32_top.vhd:329:5:@0ms:(assertion note): [NEORV32] The NEORV32 RISC-V Processor (v1.11.6.0), github.com/stnolting/neorv32
 ../rtl/core/neorv32_top.vhd:335:5:@0ms:(assertion note): [NEORV32] Processor Configuration: CPU (smp-dual-core) IMEM-ROM DMEM I-CACHE D-CACHE XBUS CLINT GPIO UART0 UART1 SPI SDI TWI TWD PWM WDT TRNG CFS NEOLED GPTMR ONEWIRE DMA SLINK SYSINFO OCD OCD-AUTH OCD-HWBP
 ../rtl/core/neorv32_top.vhd:388:5:@0ms:(assertion note): [NEORV32] BOOT_MODE_SELECT = 2: booting IMEM image
-../rtl/core/neorv32_cpu.vhd:130:5:@0ms:(assertion note): [NEORV32] CPU ISA: rv32iabmux_zaamo_zalrsc_zba_zbb_zbkb_zbkc_zbkx_zbs_zicntr_zicond_zicsr_zifencei_zihpm_zfinx_zkn_zknd_zkne_zknh_zks_zksed_zksh_zkt_zmmul_zxcfu_sdext_sdtrig_smpmp
+../rtl/core/neorv32_cpu.vhd:130:5:@0ms:(assertion note): [NEORV32] CPU ISA: rv32iabmux_zaamo_zalrsc_zba_zbb_zbkb_zbkc_zbkx_zbs_zicntr_zicond_zicsr_zifencei_zihpm_zfinx_zkn_zknd_zkne_zknh_zks_zksed_zksh_zkt_zmmul_sdext_sdtrig_smpmp_xcfu
 ../rtl/core/neorv32_cpu.vhd:168:5:@0ms:(assertion note): [NEORV32] CPU tuning options: fast_mul fast_shift
 ../rtl/core/neorv32_cpu.vhd:175:5:@0ms:(assertion warning): [NEORV32] Assuming this is a simulation.
 ../rtl/core/neorv32_imem.vhd:61:3:@0ms:(assertion note): [NEORV32] Implementing processor-internal IMEM as pre-initialized ROM.

diff --git a/rtl/core/neorv32_cpu.vhd b/rtl/core/neorv32_cpu.vhd
@@ -52,11 +52,11 @@ entity neorv32_cpu is
     RISCV_ISA_Zksed     : boolean;                        -- ShangMi hash extension
     RISCV_ISA_Zksh      : boolean;                        -- ShangMi block cipher extension
     RISCV_ISA_Zmmul     : boolean;                        -- multiply-only M sub-extension
-    RISCV_ISA_Zxcfu     : boolean;                        -- custom (instr.) functions unit
     RISCV_ISA_Sdext     : boolean;                        -- external debug mode extension
     RISCV_ISA_Sdtrig    : boolean;                        -- trigger module extension
     RISCV_ISA_Smcntrpmf : boolean;                        -- counter privilege-mode filtering
     RISCV_ISA_Smpmp     : boolean;                        -- physical memory protection
+    RISCV_ISA_Xcfu      : boolean;                        -- custom (instr.) functions unit
     -- Tuning Options --
     CPU_TRACE_EN        : boolean;                        -- enable CPU execution trace generator
     CPU_CONSTT_BR_EN    : boolean;                        -- constant-time branches
@@ -181,11 +181,11 @@ begin
       cond_sel_string_f(RISCV_ISA_Zksh,      "_zksh",      "" ) &
       cond_sel_string_f(riscv_zkt_c,         "_zkt",       "" ) &
       cond_sel_string_f(RISCV_ISA_Zmmul,     "_zmmul",     "" ) &
-      cond_sel_string_f(RISCV_ISA_Zxcfu,     "_zxcfu",     "" ) &
       cond_sel_string_f(RISCV_ISA_Sdext,     "_sdext",     "" ) &
       cond_sel_string_f(RISCV_ISA_Sdtrig,    "_sdtrig",    "" ) &
       cond_sel_string_f(RISCV_ISA_Smcntrpmf, "_smcntrpmf", "" ) &
-      cond_sel_string_f(RISCV_ISA_Smpmp,     "_smpmp",     "" )
+      cond_sel_string_f(RISCV_ISA_Smpmp,     "_smpmp",     "" ) &
+      cond_sel_string_f(RISCV_ISA_xcfu,      "_xcfu",      "" )
       severity note;
 
     -- CPU tuning options --
@@ -273,11 +273,11 @@ begin
     RISCV_ISA_Zksh      => RISCV_ISA_Zksh,      -- ShangMi hash extension
     RISCV_ISA_Zkt       => riscv_zkt_c,         -- data-independent execution time for cryptography operations available
     RISCV_ISA_Zmmul     => RISCV_ISA_Zmmul,     -- multiply-only M sub-extension
-    RISCV_ISA_Zxcfu     => RISCV_ISA_Zxcfu,     -- custom (instr.) functions unit
     RISCV_ISA_Sdext     => RISCV_ISA_Sdext,     -- external debug mode extension
     RISCV_ISA_Sdtrig    => RISCV_ISA_Sdtrig,    -- trigger module extension
     RISCV_ISA_Smcntrpmf => RISCV_ISA_Smcntrpmf, -- counter privilege-mode filtering
     RISCV_ISA_Smpmp     => RISCV_ISA_Smpmp,     -- physical memory protection
+    RISCV_ISA_Xcfu      => RISCV_ISA_Xcfu,      -- custom (instr.) functions unit
     -- Tuning Options --
     CPU_CONSTT_BR_EN    => CPU_CONSTT_BR_EN     -- constant-time branches
   )
@@ -418,7 +418,7 @@ begin
     RISCV_ISA_Zksed  => RISCV_ISA_Zksed,  -- ShangMi block cipher extension
     RISCV_ISA_Zksh   => RISCV_ISA_Zksh,   -- ShangMi hash extension
     RISCV_ISA_Zmmul  => RISCV_ISA_Zmmul,  -- multiply-only M sub-extension
-    RISCV_ISA_Zxcfu  => RISCV_ISA_Zxcfu,  -- custom (instr.) functions unit
+    RISCV_ISA_Xcfu   => RISCV_ISA_Xcfu,   -- custom (instr.) functions unit
     -- Tuning Options --
     FAST_MUL_EN      => CPU_FAST_MUL_EN,  -- use DSPs for M extension's multiplier
     FAST_SHIFT_EN    => CPU_FAST_SHIFT_EN -- use barrel shifter for shift operations

diff --git a/rtl/core/neorv32_cpu_alu.vhd b/rtl/core/neorv32_cpu_alu.vhd
@@ -34,7 +34,7 @@ entity neorv32_cpu_alu is
     RISCV_ISA_Zksed  : boolean; -- ShangMi block cipher extension
     RISCV_ISA_Zksh   : boolean; -- ShangMi hash extension
     RISCV_ISA_Zmmul  : boolean; -- multiply-only M sub-extension
-    RISCV_ISA_Zxcfu  : boolean; -- custom (instr.) functions unit
+    RISCV_ISA_Xcfu   : boolean; -- custom (instr.) functions unit
     -- Tuning Options --
     FAST_MUL_EN      : boolean; -- use DSPs for M extension's multiplier
     FAST_SHIFT_EN    : boolean  -- use barrel shifter for shift operations
@@ -264,10 +264,10 @@ begin
     cp_valid(3)  <= '0';
   end generate;
 
-  -- CUSTOM-Opcode Co-Processor: Custom Functions Unit ('Zxcfu' ISA Extension) --------------
+  -- CUSTOM-Opcode Co-Processor: Custom Functions Unit ('Xcfu' ISA Extension) ---------------
   -- -------------------------------------------------------------------------------------------
   neorv32_cpu_alu_cfu_enabled:
-  if RISCV_ISA_Zxcfu generate
+  if RISCV_ISA_Xcfu generate
     neorv32_cpu_alu_cfu_inst: entity neorv32.neorv32_cpu_alu_cfu
     port map (
       -- global control --
@@ -310,7 +310,7 @@ begin
   end generate;
 
   neorv32_cpu_alu_cfu_disabled:
-  if not RISCV_ISA_Zxcfu generate
+  if not RISCV_ISA_Xcfu generate
     cfu_done     <= '0';
     cfu_res      <= (others => '0');
     cfu_busy     <= '0';

diff --git a/rtl/core/neorv32_cpu_control.vhd b/rtl/core/neorv32_cpu_control.vhd
@@ -54,11 +54,11 @@ entity neorv32_cpu_control is
     RISCV_ISA_Zksh      : boolean; -- ShangMi hash extension
     RISCV_ISA_Zkt       : boolean; -- data-independent execution time (for cryptography operations)
     RISCV_ISA_Zmmul     : boolean; -- multiply-only M sub-extension
-    RISCV_ISA_Zxcfu     : boolean; -- custom (instr.) functions unit
     RISCV_ISA_Sdext     : boolean; -- external debug mode extension
     RISCV_ISA_Sdtrig    : boolean; -- trigger module extension
     RISCV_ISA_Smcntrpmf : boolean; -- counter privilege-mode filtering
     RISCV_ISA_Smpmp     : boolean; -- physical memory protection
+    RISCV_ISA_Xcfu      : boolean; -- custom (instr.) functions unit
     -- Tuning Options --
     CPU_CONSTT_BR_EN    : boolean  -- constant-time branches
   );
@@ -1211,7 +1211,7 @@ begin
             csr_rdata(0)  <= '1';                                   -- Zicsr: CSR access (always enabled)
             csr_rdata(1)  <= '1';                                   -- Zifencei: instruction stream sync. (always enabled)
             csr_rdata(2)  <= bool_to_ulogic_f(RISCV_ISA_Zmmul);     -- Zmmul: mul/div
-            csr_rdata(3)  <= bool_to_ulogic_f(RISCV_ISA_Zxcfu);     -- Zxcfu: custom instructions
+            csr_rdata(3)  <= bool_to_ulogic_f(RISCV_ISA_Xcfu);      -- Xcfu: custom instructions
             csr_rdata(4)  <= bool_to_ulogic_f(RISCV_ISA_Zkt);       -- Zkt: data independent execution latency
             csr_rdata(5)  <= bool_to_ulogic_f(RISCV_ISA_Zfinx);     -- Zfinx: FPU using x registers
             csr_rdata(6)  <= bool_to_ulogic_f(RISCV_ISA_Zicond);    -- Zicond: integer conditional operations

diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd
@@ -20,7 +20,7 @@ package neorv32_package is
 
   -- Architecture Constants -----------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01120705"; -- hardware version
+  constant hw_version_c  : std_ulogic_vector(31 downto 0) := x"01120706"; -- hardware version
   constant int_bus_tmo_c : natural := 16; -- internal bus timeout window; has to be a power of two
   constant alu_cp_tmo_c  : natural := 9;  -- log2 of max ALU co-processor execution cycles
 
@@ -863,8 +863,8 @@ package neorv32_package is
       RISCV_ISA_Zknh      : boolean                        := false;
       RISCV_ISA_Zksed     : boolean                        := false;
       RISCV_ISA_Zksh      : boolean                        := false;
-      RISCV_ISA_Zxcfu     : boolean                        := false;
       RISCV_ISA_Smcntrpmf : boolean                        := false;
+      RISCV_ISA_Xcfu      : boolean                        := false;
       -- Tuning Options --
       CPU_CONSTT_BR_EN    : boolean                        := false;
       CPU_FAST_MUL_EN     : boolean                        := false;

diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd
@@ -61,8 +61,8 @@ entity neorv32_top is
     RISCV_ISA_Zksed     : boolean                        := false;         -- ShangMi block cipher extension
     RISCV_ISA_Zksh      : boolean                        := false;         -- ShangMi hash extension
     RISCV_ISA_Zmmul     : boolean                        := false;         -- multiply-only M sub-extension
-    RISCV_ISA_Zxcfu     : boolean                        := false;         -- custom (instr.) functions unit
     RISCV_ISA_Smcntrpmf : boolean                        := false;         -- counter privilege-mode filtering
+    RISCV_ISA_Xcfu      : boolean                        := false;         -- custom (instr.) functions unit
 
     -- Tuning Options --
     CPU_CONSTT_BR_EN    : boolean                        := false;         -- enable constant-time branches
@@ -514,11 +514,11 @@ begin
       RISCV_ISA_Zksed     => RISCV_ISA_Zksed,
       RISCV_ISA_Zksh      => RISCV_ISA_Zksh,
       RISCV_ISA_Zmmul     => RISCV_ISA_Zmmul,
-      RISCV_ISA_Zxcfu     => RISCV_ISA_Zxcfu,
       RISCV_ISA_Sdext     => OCD_EN,
       RISCV_ISA_Sdtrig    => cpu_sdtrig_en_c,
       RISCV_ISA_Smcntrpmf => RISCV_ISA_Smcntrpmf,
       RISCV_ISA_Smpmp     => cpu_smpmp_en_c,
+      RISCV_ISA_Xcfu      => RISCV_ISA_Xcfu,
       -- Tuning Options --
       CPU_TRACE_EN        => trace_en_c,
       CPU_CONSTT_BR_EN    => CPU_CONSTT_BR_EN,

diff --git a/rtl/system_integration/neorv32_vivado_ip.tcl b/rtl/system_integration/neorv32_vivado_ip.tcl
@@ -288,7 +288,7 @@ proc setup_ip_gui {} {
     { RISCV_ISA_Zibi   {Zibi - Branch with immediate-comparison}            {} }
     { RISCV_ISA_Zicond {Zicond - Conditional-move instructions}             {} }
     { RISCV_ISA_Zimop  {Zimop - May-be-operation}                           {} }
-    { RISCV_ISA_Zxcfu  {Zxcfu - Custom-instructions unit (user-defined)}    {} }
+    { RISCV_ISA_Xcfu   {Xcfu - Custom-instructions unit (user-defined)}     {} }
   }
 
   set group [add_group $page {Physical Memory Protection (PMP)}]

diff --git a/rtl/system_integration/neorv32_vivado_ip.vhd b/rtl/system_integration/neorv32_vivado_ip.vhd
@@ -62,8 +62,8 @@ entity neorv32_vivado_ip is
     RISCV_ISA_Zknh        : boolean                        := false;
     RISCV_ISA_Zksed       : boolean                        := false;
     RISCV_ISA_Zksh        : boolean                        := false;
-    RISCV_ISA_Zxcfu       : boolean                        := false;
     RISCV_ISA_Smcntrpmf   : boolean                        := false;
+    RISCV_ISA_Xcfu        : boolean                        := false;
     -- Tuning Options --
     CPU_CONSTT_BR_EN      : boolean                        := false;
     CPU_FAST_MUL_EN       : boolean                        := false;
@@ -396,8 +396,8 @@ begin
     RISCV_ISA_Zknh      => RISCV_ISA_Zknh,
     RISCV_ISA_Zksed     => RISCV_ISA_Zksed,
     RISCV_ISA_Zksh      => RISCV_ISA_Zksh,
-    RISCV_ISA_Zxcfu     => RISCV_ISA_Zxcfu,
     RISCV_ISA_Smcntrpmf => RISCV_ISA_Smcntrpmf,
+    RISCV_ISA_Xcfu      => RISCV_ISA_Xcfu,
     -- Extension Options --
     CPU_CONSTT_BR_EN    => CPU_CONSTT_BR_EN,
     CPU_FAST_MUL_EN     => CPU_FAST_MUL_EN,