v1.11.6

What's Changed

• 🐛 fix byte-enable bus signal for instruction fetch accesses by @stnolting in #1272
• minor rtl edits and cleanups by @stnolting in #1273
• ⚠️ CFS IO rework by @stnolting in #1274
• ⚠️ remove CRC module by @stnolting in #1275
• Rework IMEM & DMEM RAM style by @stnolting in #1277
• [cpu] rework instruction trap logic by @stnolting in #1278
• 🧪 rework DMA controller by @stnolting in #1279
• ⚠️ Rename IMEM/DMEM configuration generics by @stnolting in #1280
• Add optional IMEM/DMEM output register stages by @stnolting in #1281

Full Changelog: v1.11.5...v1.11.6