v1.11.6
What's Changed
- ๐ fix byte-enable bus signal for instruction fetch accesses by @stnolting in #1272
- minor rtl edits and cleanups by @stnolting in #1273
โ ๏ธ CFS IO rework by @stnolting in #1274โ ๏ธ remove CRC module by @stnolting in #1275- Rework IMEM & DMEM RAM style by @stnolting in #1277
- [cpu] rework instruction trap logic by @stnolting in #1278
- ๐งช rework DMA controller by @stnolting in #1279
โ ๏ธ Rename IMEM/DMEM configuration generics by @stnolting in #1280- Add optional IMEM/DMEM output register stages by @stnolting in #1281
Full Changelog: v1.11.5...v1.11.6