v1.11.7

What's Changed

• [cpu] Minor rtl optimizations and cleanups by @stnolting in #1283
• upgrade TRNG to neoTRNG v3.3 by @stnolting in #1284
• ✨ on chip debugger: add semihosting support by @stnolting in #1285
• ⚠️ combine SLINK's RX and TX interrupts into a single interrupt by @stnolting in #1286
• ✨ add TRNG interrupt by @stnolting in #1287
• ⚠️ rework UART "TX FIFO full" status flag by @stnolting in #1288
• ⚠️ combine UART's RX and TX interrupts into a single interrupt by @stnolting in #1289
• Minor rtl edits and optimizations by @stnolting in #1291
• Remove enable logic for SoC-wide clock generator by @stnolting in #1292

Full Changelog: v1.11.6...v1.11.7