64-bit ALU Verification, Part I #70
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* import RV64IM * revert to regidx from SailM after BitVec instance fix
added 8 commits
August 2, 2025 00:11
dtumad
reviewed
Aug 4, 2025
SP1Chips/SubChip.lean
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| (cstrs : (constraints Main).allHold) | ||
| (h_is_real : Main[32] = 1) | ||
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| def spec_add (rs2 rs1 rd : regidx) : SailM Unit := do |
SP1Chips/SubChip.lean
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| open Sail | ||
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| theorem correct_add |
GZGavinZhao
reviewed
Aug 6, 2025
SP1Chips/ShiftRightChip.lean
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| let op_a := sp1_op_a Main cstrs (srl_real Main srl) | ||
| -- TODO(gzgz): we can obtain this from the constraint compiler | ||
| -- This comes from the Interaction.state in CPUState | ||
| Sail.writeReg Register.nextPC (Word.toBitVec64 #v[Main[3], Main[4], Main[5], 0] + 4) |
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The value that's actually being written is Word.toBitVec64 #v[Main[3] + 4, Main[4], Main[5], 0]. Could you please update all of your chip proof to use this instead? The equivalence holds using something like this:
have : (↑(Main[3]$ + 4) + ↑Main[4]$ <<< 16 + ↑Main[5]$ <<< 32 : ℕ) = ↑Main[3]$ + ↑Main[4]$ <<< 16 + ↑Main[5]$ <<< 32 + 4 := by
simp [Fin.add_def]
rw [Nat.mod_eq_of_lt (by clear * - h_pc0; linarith)]
ring_nf
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I'm not sure what you mean here. Actually being written by whom? The Rust code of the reader?
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In any case, done.
added 11 commits
August 7, 2025 10:10
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This PR introduces the following specifications and proofs:
IsEqualWord,IsZero,IsZeroWord,LtOperationSigned,LtOperationUnsigned,U16Compare,Add,Addw,Sub,Subw,U16MSB, andU16toU8Unsafeoperations;ALUType,CpuState,IType, andRTypereaders; andDiv- andRem-related ones.It also provides the proof of the axiom previously introduced in
LtOperationSigned.I would suggest that the proofs for other operations, readers, and opcodes that have appeared in the meantime be revisited in the style of the ones I've proven. In particular, the shift-right operation has the most streamlined structure that simplifies chip proofs greatly.