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Unable to build just the ice-v CPU

Status: Open.

#270 In sylefeb/Silice;

· MrJake222 opened on May 31, 2024

Enhancement of declaration of and usage of always assignments

Status: Open.

#269 In sylefeb/Silice;

· rob-ng15 opened on Apr 15, 2024

$$ directives in board file Verilog are not ignored in code disabled by preprocessor test or /* */

enhancementNew feature or requestNew feature or request

Status: Open.

#268 In sylefeb/Silice;

· FPGAEveryday opened on Apr 13, 2024

Enhancement of declaration of bram/brom/simple_dualport_bram/dualport_bram

enhancementNew feature or requestNew feature or request

Status: Open.

#267 In sylefeb/Silice;

· rob-ng15 opened on Apr 8, 2024

Documentation: possible typo in Silice/learn-silice/Documentation.md?

documentationImprovements or additions to documentationImprovements or additions to documentation

Status: Open.

#263 In sylefeb/Silice;

· conversy opened on Jan 17, 2024

inouts cannot be bound using a bit-select syntax

enhancementNew feature or requestNew feature or request

Status: Open.

#258 In sylefeb/Silice;

· sylefeb opened on Dec 30, 2023

Can't compile Silice on Arch Linux

Status: Open.

#255 In sylefeb/Silice;

· Popolon opened on Aug 23, 2023

uart_tx and uart_rx seem to have wrong direction in the Verilog framework file for the ECPIX5-Board

Status: Open.

#254 In sylefeb/Silice;

· at91rm9200 opened on Aug 19, 2023

Error initialising bram not brom

Status: Open.

#251 In sylefeb/Silice;

· rob-ng15 opened on May 12, 2023

Name shadowing

Status: Open.

#250 In sylefeb/Silice;

· sylefeb opened on Mar 28, 2023

Unused states that remain and cycles that could be avoided

Status: Open.

#248 In sylefeb/Silice;

· sylefeb opened on Mar 11, 2023

Empty FSM states could be optimized

Status: Open.

#247 In sylefeb/Silice;

· suarezvictor opened on Mar 11, 2023