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Merge pull request #1227 from fk-sc/fk-sc/type-safe-enum

target/riscv: make mem_access_result_t enum type safe

sc-riscv-v0.10.0-1974

FIX(src/target/riscv/riscv.c): CSR_MCOUNTEREN is not available w/o U or S

sc-riscv-0.10.0-1972

• FIX(src/server/gdb_server.c): infinite loop in gdb_generate_reg_type_description for REG_TYPE_CLASS_STRUCT
• FIX(src/target/sc_riscv32/sc_rv32_common.c) update RISC-V features, adjust enabling of CSRs according to misa
• FIX(src/target/sc_riscv32/sc_rv32_common.c) relaxed (poll based only) update state after resume
• chore(src/target/sc_riscv32/sc_rv32_common.c) using target_name, target_state_name, debug_reason_name

Сanonical register names

FIX: replace ABI register aliases by canonical register names
CSRs enabling based on misa.
FIX: syntacore_riscv32 targets: relaxed (poll-based only) state update after resume (slow-down events to gdb)

2 scr4 cores with separate TAPs

scr4-2TAPs

chore(src/target/riscv/riscv.h,src/target/riscv/riscv.c) remove unuse…