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The TT runners have more disk space, so this step is not required. Signed-off-by: Joel Stanley <joel@jms.id.au>
To start with, build a glibc toolchain on 24.04 only. Signed-off-by: Joel Stanley <joel@jms.id.au>
Github CI was having trouble checking out some of the repositries. Given we do not use them, remove them from the config. Signed-off-by: Joel Stanley <joel@jms.id.au>
Remove unused test-sim and build-multilib. Signed-off-by: Joel Stanley <joel@jms.id.au>
The TT runners appear to use something else. Signed-off-by: Joel Stanley <joel@jms.id.au>
22.04 only for now. Signed-off-by: Joel Stanley <joel@jms.id.au>
Point to the Tenstorrent forks for projects where downstream development will be staged. Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Like the existing TT toolchain, build one tarball with gcc, clang and qemu. The matrix is just a vector now, but retain the structure to ease rebasing on upstream changes. Note that rv64imafdc is the equivalent of rv64gc. Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Pulls in this from GCC:
commit 4275518a06333109b6423c4eb15dd86a6479cef5
Author: Peter Bergner <bergner@tenstorrent.com>
Date: Mon Sep 22 12:17:26 2025 -0500
RISC-V: Add missing define_insn_reservation to tt-ascalon-d8.md [PR121982]
The tt-ascalon-d8's pipeline description has reservations for 16-bit, 32-bit
and 64-bit vector integer divides, but was missing a reservation for 8-bit
vector integer divides, leading to an ICE. Add the missing reservation.
2025-09-22 Peter Bergner <bergner@tenstorrent.com>
gcc/
PR target/121982
* config/riscv/tt-ascalon-d8.md (tt_ascalon_d8_vec_idiv_byte): New
define_insn_reservation.
gcc/testsuite/
PR target/121982
* gcc.target/riscv/pr121982.c: New test.
Signed-off-by: Peter Bergner <bergner@tenstorrent.com>
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